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cyw88335 single-chip 5g wi-fi ieee 802.11ac mac/baseband/radio with integrated blue tooth 4.1 for automotive applications cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-15057 rev. *b revised may 8, 2017 the cypress cyw88335 single-chip device provides the highest level of integration for automotive in-vehicle infotainment connec - tivity systems with integrated single-stream ieee 802.11ac mac/baseband/radio, bluetooth 4.1. in ieee 802.11ac mode, the wlan operation supports rates of mcs0?mcs9 (up to 256 qam) in 20 mhz, 40 mhz, and 80 mhz channels for data rates up to 433.3 mbps. in addition, all the rates specified in ieee 802.11a/b/g/n are su pported. included on-chip are 2.4 g hz and 5 ghz transmit amplifi ers, and receive low-noise amplifiers. optional external pas, lnas, and antenna diversity are also supported. the cyw88335 offers an sdio v3.0 interface for high speed 802.11ac con nectivity. the bluetooth host controller is interfaced over a 4-wire high speed uart and includes pcm for audio. the cyw88335 brings the latest mobile connectivity technology to automotive infotainment, telema tics and rear seat entertainmen t. offering automotive grade 3 (?40c to +85c) temperature perfo rmance, the cyw88335 is tested to aecq100 environmental stress guidelines and manufactured in iso9001 and ts16949 certified facilities. the cyw88335 implements highly sophisticated enhanc ed collaborative coexistence hardware mechanisms and algorithms, which ensure that wlan and bluetooth collaboration is optimized for ma ximum performance. in addition, coexistence support for externa l radios (such as lte cellular, gps, and wimax) is provided via an external interface. as a result, enhanced overall quality for simultaneous voice, video, and data transmission is achieved. cypress part numbering scheme cypress is converting the acquired iot part numbers from broadcom to the cypress par t numbering scheme. due to this conversion, there is no change in form, fit, or function as a result of offe ring the device with cypress part number marking. the table pro vides cypress ordering part number that matches an existing iot part number. acronyms and abbreviations in most cases, acronyms and abbreviations are defined on first use. for a comprehensive list of acronyms and other terms used in cypress documents, go to http://www.cypress.com/glossary . features ieee 802.11x key features ieee 802.11ac compliant. single-stream spatial multiplexing up to 433.3 mbps data rate. supports 20, 40, and 80 mhz channels with optional sgi (256 qam modulation). full ieee 802.11a/b/ g/n legacy compatibi lity with enhanced performance. tx and rx low-density parity check (ldpc) support for improved range and power efficiency. supports rx space-time block coding (stbc) supports ieee 802.11ac/n beamforming. on-chip power amplifiers and low-noise amplifiers for both bands. support for optional front-end modules (fem) with external pas and lnas shared bluetooth and wlan receive signal path eliminates the need for an external power splitter while maintaining excellent sensitivity for both bluetooth and wlan. internal fractional npll allows support for a wide range of reference clock frequencies supports ieee 802.15.2 external coexistence interface to optimize bandwidth utilization with other co-located wireless technologies such as lte, gps, or wimax supports standard sdio v3.0 (including ddr50 mode at 50 mhz and sdr104 mode at 208 mhz, 4-bit and 1-bit), and gspi (48 mhz) host interfaces. backward compatible with sdio v2.0 host interfaces. integrated armcr4 ? processor with tightly coupled memory for complete wlan subsystem fu nctionality, minimizing the need to wake up the applications processor for standard wlan functions. this allows for further minimization of power consumption, while maintaining t he ability to field upgrade with future features. on-chip memory includes 768 kb sram and 640 kb rom. onedriver ? software architecture for easy migration from existing embedded wlan and bluetooth devices as well as future devices. table 1. mapping table for part number between broadcom and cypress broadcom part number cypress part number BCM88335 cyw88335 BCM88335l2cubg cyw88335l2cubg
cyw88335 document number: 002-15057 rev. *b page 2 of 110 bluetooth key features complies with bluetooth core specification version 4.1 for automotive applications with provisions for supporting future specifications. bluetooth class 1 or class 2 transmitter operation. supports extended synchronous connections (esco), for enhanced voice quality by allowing for retransmission of dropped packets. adaptive frequency hopping (afh) for reducing radio frequency interference. interface support, host controller interface (hci) using a high- speed uart interface and pcm for audio data. supports multiple simultaneous advanced audio distribution profiles (a2dp) for stereo sound. automatic frequency detection fo r standard crystal and tcxo values. supports low energy host wake-up for long term system sleep capability. general features supports battery voltage range fr om 3.0v to 4.8v supplies with internal switching regulator. programmable dynamic power management otp: 502 bytes of user-accessible memory nine gpios package options: ? 145 ball wlbga (4.87 mm 5.413 mm, 0.4 mm pitch) security: ? wpa ? and wpa2 ? (personal) support for powerful encryp- tion and authentication ? aes and tkip in hardware for faster data encryption and ieee 802.11i compatibility ? reference wlan subsystem provides cisco ? compatible extensions (ccx, ccx 2.0, ccx 3.0, ccx 4.0, ccx 5.0) ? reference wlan subsystem prov ides wi-fi protected setup (wps) worldwide regulatory support: global products supported with worldwide homologated design. figure 1. functional block diagram iot resources cypress provides a wealth of data at http://www.cypress.co m/internet-things-iot to help you to select the right iot device for your design, and quickly and effectively integrat e the device into your design. cypress pr ovides customer access to a wide range of information, including technical documentat ion, schematic diagrams, product bill of ma terials, pcb layout information, and soft ware updates. customers can acquire technica l documentation and softwa re from the cypress support community website ( http:// community.cypress.com/ ). fem or t/r switch vio vbat 5 ghz wlan tx 5 ghz wlan rx 2.4 ghz wlan tx 2.4 ghz wlan/bt rx bluetooth tx wlan host i/f bluetooth host i/f wl_reg_on sdio*/spi bt_reg_on uart bt_dev_wake bt_host_wake cbf i 2 s clk_req pcm coex external coexistence i/f fem or t/r switch cyw88335
document number: 002-15057 rev. *b page 3 of 110 cyw88335 contents 1. overview ........................................................................ 4 1.1 overview ............................................................... 4 1.2 features ................................................................ 6 1.3 standards compliance .......................................... 6 1.4 automotive usage model . ..................................... 7 2. power supplies an d power management ................... 8 2.1 power supply topology ........................................ 8 2.2 pmu features ....................................................... 8 2.3 wlan power management . .............. ........... ....... 10 2.4 pmu sequencing ............. .............. .............. ....... 10 2.5 power-off shutdown ........................................... 11 2.6 power-up/power-down/rese t circuits ............... 11 3. frequency references ............................................... 12 3.1 crystal interface and clock generation .............. 12 3.2 external frequency refer ence ............................ 12 3.3 frequency selection ......... .............. .............. ....... 14 3.4 external 32.768 khz low-power oscillator ......... 14 4. bluetooth subsystem overview ................................ 15 4.1 features .............................................................. 15 4.2 bluetooth radio ................................................... 16 5. bluetooth baseband core ... .............. .............. .......... 17 5.1 bluetooth 4.1 features ........................................ 17 5.2 bluetooth low energy ......................................... 17 5.3 link control layer ............................................... 17 5.4 test mode support ........... .............. .............. ....... 18 5.5 bluetooth power management unit ......... ............ 18 5.6 adaptive frequency hoppin g .............................. 22 5.7 advanced bluetooth/wlan coexistence ............ 22 5.8 fast connection (interlaced page and inquiry scans) ................ .............. .............. ....... 22 6. microprocessor and memory unit for bluetooth ..... 23 6.1 overview ............................................................. 23 6.2 ram, rom, and patch memory .......................... 23 6.3 reset ................................................................... 23 7. bluetooth peripheral transport unit ........................ 24 7.1 pcm interface ..................................................... 24 7.2 uart interface .................................................... 30 7.3 i 2 s interface ........................................................ 31 8. wlan global functions ............................................ 34 8.1 wlan cpu and memory subsystem ...... ............ 34 8.2 one-time programmable memory ...................... 34 8.3 gpio interface .................................................... 34 8.4 external coexistence interface ........................... 35 8.5 uart interface .................................................... 35 8.6 jtag interface .................................................... 35 9. wlan host interfaces ................................................ 36 9.1 sdio v3.0 ............................................................ 36 9.2 generic spi mode ............................................... 37 10. wireless lan mac and phy ................................... 45 10.1 ieee 802.11ac mac ...... .............. .............. ....... 45 10.2 ieee 802.11ac phy ....... .............. .............. ....... 48 11. wlan radio subsystem ......................................... 50 11.1 receiver path .................................................... 50 11.2 transmit path .................................................... 50 11.3 calibration ......................................................... 50 12. pinout and signal descriptions .............................. 52 12.1 ball maps ........................................................... 52 12.2 signal descriptions ........ .................................... 53 12.3 wlan gpio signals an d strapping options .... 58 12.4 gpio/sdio alternative signal functions .......... 61 12.5 i/o states .......................................................... 62 13. dc characteristics ................................................... 65 13.1 absolute maxi mum ratings ............................... 65 13.2 environmental ratings .. .................................... 65 13.3 electrostatic discharge specifications .............. 65 13.4 recommended operating conditions and dc characteristics ............................................ 66 14. bluetooth rf specifications .................................... 68 15. wlan rf specifications .......................................... 74 15.1 introduction ........................................................ 74 15.2 2.4 ghz band general rf specifications ........ 74 15.3 wlan 2.4 ghz receiver performance specifications ................................................... 75 15.4 wlan 2.4 ghz transmitter performance specifications ................................................... 79 15.5 wlan 5 ghz receiver performance specifications ................................................... 80 15.6 wlan 5 ghz transmitter performance specifications ................................................... 83 15.7 general spurious emissions specifications ...... 84 16. internal regulator electri cal specifications .......... 85 16.1 core buck switching re gulator ......................... 85 16.2 3.3v ldo (ldo3p3) ......................................... 86 16.3 2.5v ldo (btldo2p5) ..................................... 87 16.4 cldo ................................................................ 88 16.5 lnldo .............................................................. 89 17. system power consumption ................................... 90 17.1 wlan current consumption ............................. 90 17.2 bluetooth current consumption ........................ 91 18. interface timing and ac characteristics ............... 92 18.1 sdio/gspi timing ............................................. 92 18.2 jtag timing .................................................. 101 19. power-up sequence and timing ........................... 102 19.1 sequencing of reset and regulator control signals ............................... 102 20. package information ............ .............. .............. ...... 105 20.1 package thermal characte ristics ....... ............ 105 20.2 junction temperature estimation and psi jt versus theta jc .................................. 105 20.3 environmental characteri stics ......................... 105 21. mechanical information ......................................... 106 22. ordering information .............................................. 108 23. references ........ ...................................................... 108 document history ........................................................ 109 sales, solutions, and legal information ................... 110
document number: 002-15057 rev. *b page 4 of 110 cyw88335 1. overview 1.1 overview the cypress cyw88335 single-chip device provides the highest level of integration for automotive in-vehicle infotainment wirele ss connectivity systems, with integrated ieee 802.11 a/b/g/n/ac mac/baseband/radio, and bl uetooth 4.1 + enhanced data rate (edr). it provides a small form-factor solution wit h minimal external component s to drive down cost for ma ss volumes and allows for pl atform flexibility in size, form, and function. the following figure shows the interconnect of all the major ph ysical blocks in the cyw88335 and their associated external inte rfaces, which are described in greater detail in the following sections.
document number: 002-15057 rev. *b page 5 of 110 cyw88335 figure 2. cyw88335 block diagram bluetooth wlan uart i2s pcm port control registers dma jtag master gpio timers wd pause ahb2apb ahb bus matrix ram rom armcm3 wlan master slave rx/tx ble lcu apu bluerf pmu clb fem or sp3t fem or spdt diplexer modem bluetooth rf 2.4 ghz/5 ghz 802.11ac dual-band radio 1 x 1 802.11ac phy dot11mac (d11) chip common otp nic-301 axi backplane axi2ahb ahb2axi armcr4 tcm ram768kb rom640kb sdiod axi2apb gci seci uart and gci-gpios wlan ram sharing wlan bt access gci coex i/f shared lna control and other coex i/fs vbat wl_reg_on bt_reg_on bt_host_wake bt_dev_wake uart pcm i 2 s other gpios bt pa 32 khz external lpo xtal rf switch controls sdio 3.0 wl_host_wake wl_dev_wake jtag other gpios 2.4 ghz 5 ghz
document number: 002-15057 rev. *b page 6 of 110 cyw88335 1.2 features the cyw88335 supports the following features: ieee 802.11a/b/g/n/ac dual-b and radio with virtual-simu ltaneous dual-b and operation bluetooth v4.1 + edr with integrated class 1 pa concurrent bluetooth and wlan operation on-chip wlan driver execution capabl e of supporting ieee 802.11 functionality wlan host interface options: ? sdio v3.0 (1-bit/4-bit)?up to 20 8 mhz clock rate in sdr104 mode ? gspi?up to 48 mhz clock rate bt host digital interface (which can be us ed concurrently with the above interfaces): ? uart (up to 4 mbps) eci?enhanced coexistence support, ability to coordi nate bt sco transmissions around wlan receptions i 2 s/pcm for bt audio hci high-speed uart (h4, h4+, h5) transport support wideband speech support (16 bits linear data, msb first, left just ified at 4k samples/s for transparent air coding, both throug h i 2 s and pcm interface) bluetooth smartaudio ? technology improves voice and music quality for automotive applications bluetooth low-power inquiry and page scan bluetooth low energy (ble) support bluetooth packet loss concealment (plc) bluetooth wide band speech (wbs) audio rate-matching algorithms 1.3 standards compliance the cyw88335 supports the following standards: bluetooth 2.1 + edr bluetooth 3.0 bluetooth 4.1 (bluetooth low energy) ieee802.11ac single-stream mandatory and optional requirements for 20 mhz, 40 mhz, and 80 mhz channels ieee 802.11n?handheld device class (section 11) ieee 802.11a ieee 802.11b ieee 802.11g ieee 802.11d ieee 802.11h ieee 802.11i
document number: 002-15057 rev. *b page 7 of 110 cyw88335 security: ? wep ? wpa ? personal ? wpa2 ? personal ? wmm ? wmm-ps (u-apsd) ? wmm-sa ? aes (hardware accelerator) ? tkip (hw accelerator) ? ckip (sw support) proprietary protocols: ? ccxv2 ? ccxv3 ? ccxv4 ? ccxv5 ieee 802.15.2 coexistence compliance?on silicon so lution compliant with ieee 3 wire requirements the cyw88335 will support the following future drafts/standards: ieee 802.11r?fast roaming (between aps) ieee 802.11w?secure management frames ieee 802.11 extensions: ? ieee 802.11e qos enhancements (as per the wmm ? specification is already supported) ? ieee 802.11h 5 ghz extensions ? ieee 802.11i mac enhancements ? ieee 802.11k radio resource measurement 1.4 automotive usage model the cyw88335 incorporates a number of unique features to simplify integrat ion into automotive platforms. its flexible pcm and u art interfaces enable it to transparently connect with existing plat form circuits. in addition, the tcxo and lpo inputs allow the u se of existing automotive features to furt her minimize the size, power, and cost of the complete system. the pcm interface provides multiple modes of operation to support both master and slave as well as hybrid interfacing to single or multiple external codec devices. the uart interface supports hardware flow control with tight integrati on to power-control sideband signaling to support the low est power operation. the crystal oscillator interface accommodat es any of the typical reference frequencie s used by mobile platform architectures. the highly linear design of the radio transce iver ensures that the device has the lowest spurious emissions output regardless o f the state of operation. it has been fully char acterized in the global cellular bands. the transceiver design has excellent blocking and intermodulation performance in the presence of a cellular transmission (lte, gsm ? , gprs, cdma, wcdma, or iden). the cyw88335 is designed to directly interface wit h new and existing automotive platform designs.
document number: 002-15057 rev. *b page 8 of 110 cyw88335 2. power supplies and power management 2.1 power supply topology one buck regulator, multiple ldo regulators, and a power managem ent unit (pmu) are integrated into the cyw88335. all regulators are programmable via the pmu. these blocks simplify power supply design for bluetooth and wlan functions in embedded designs. a single vbat (3.0v to 4.8v dc maximum) and vio supply (1.8v to 3.3v) can be used, with all additional voltages being provided by the regulators in the cyw88335. two control signals, bt_reg_on and wl_reg_o n, are used to power up the regulators and take the respective section out of reset. the cbuck cldo and lnldo power up when any of the rese t signals are deasserted. all regulators are powered down only when both bt_reg_on and wl_reg_on are deasserted. the cldo and lnldo may be turned off and on based on the dynamic demands of the digital baseband. the cyw88335 allows for an extremely lo w power-consumption mode by completely sh utting down the cbuck, cldo, and lnldo regulators. when in this state, lpldo1 and lpldo2 (which ar e low-power linear regulators that are supplied by the system vio supply) provide the cyw88335 with all the voltages it requires, further reducing leakage currents. 2.2 pmu features vbat to 1.35v (275 ma nominal, 600 ma maxi mum) core-buck (cbuck) switching regulator vbat to 3.3v (200 ma nom inal, 450 ma maximum) ldo3p3 vbat to 2.5v (15 ma nominal , 70 ma maximum) btldo2p5 1.35v to 1.2v (100 ma nominal, 150 ma maximum) lnldo 1.35v to 1.2v (175 ma nominal, 300 ma maximum) cldo with bypass mode for deep-sleep additional internal ldos (not externally accessible)
document number: 002-15057 rev. *b page 9 of 110 cyw88335 figure 3 shows the regulators and a typical power topology. figure 3. typical power topology for the cyw88335 internal ? lnldo 80 ? ma wl ? rf ? ?afe shaded areas are internal to the cyw 88335 wl ? rf ? ?tx ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ?logen ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ? rx/lna ? (2.4 ? ghz, ? 5 ? ghz) wl ? rf ? ?xtal wl ? rf ? ?rfpll ? pfd/mmd bt ? rf bt ? class ? 1 ? pa wl ? pa/pad ? (2.4 ? ghz, ? 5 ? ghz) vddio_rf wl ? otp ? 3.3v wl ? rf ? ?vco wl ? rf ? ?cp internal ? lnldo 80 ? ma internal ? vcoldo 80 ? ma internal ? lnldo 80 ? ma xtal ? ldo 30 ? ma 1.2v 1.2v 1.2v 1.2v 1.2v lnldo 100 ? ma dfe/dfll pll/rxtx wlan ? bbpll/dfll wlan/bt/clb/top, ? always ? on wl ? otp wl ? phy wl ? digital bt ? digital wl/bt ? srams cldo peak ? 300 ? ma average ? 175 ? ma (bypass ? in ? deep ? sleep) 1.2v? 1.1v memlpldo 3 ? ma vddio btldo2p5 peak ? 70 ? ma average ? 15 ? ma 2.5v internal ? lnldo 25 ? ma internal ? lnldo 8 ? ma ldo3p3 peak ? 800?450 ? ma average ? 200 ? ma 2.5v 2.5v 3.3v 1.2v 1.35v wl_reg_on bt_reg_on lpldo1 3 ? ma core ? buck ? regulator cbuck peak ? 600 ? ma average ? 275 ? ma 1.1v vddio vbat 0.9v
document number: 002-15057 rev. *b page 10 of 110 cyw88335 2.3 wlan power management all areas of the chip design are optimized to minimize power cons umption. silicon processes and cell libraries were chosen to r educe leakage current and supply voltages. additionally, the cyw88335 inte grated ram is a high vt memory with dynamic clock control. the dominant supply current consumed by the ram is leakage curr ent only. additionally, the cyw88335 includes an advanced wlan power management unit (pmu) sequencer. the pmu sequencer provi des significant power savings by putting the cyw88335 into various power management states appropriate to the current en vironment and activities that are being performed. the power management unit enables and disables internal regulators, swit ches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. power-u p sequences are fully programmable. configurable, free-running c ounters (running at the 32.768 kh z lpo clock frequency) in the pm u sequencer are used to turn on and turn off individual regulators and power switches. clock speeds are dynamically changed (or g ated altogether) for the current mode. slower cl ock speeds are used wherever possible. the cyw88335 wlan power states are described as follows: active mode? all wlan blocks in the cyw88335 are powered up and fully functional with active carrier sensing and frame transmission and receiving. all required regulators are enabled and put in the most efficient mode based on the load current. c lock speeds are dynamically adjusted by the pmu sequencer. doze mode?the radio, analog domains, and most of the linear regulator s are powered down. the rest of the cyw88335 remains powered up in an idle state. all main clocks (pll, crystal oscillat or or tcxo) are shut down to reduce active power consumption to the minimum. the 32.768 khz lpo clock is available only for t he pmu sequencer. this condition is necessary to allow the pmu sequencer to wake up the chip and transition to active mode. in doze mode, the primar y power consumed is due to leakage current . deep-sleep mode?most of the chip, including both analog and digital domains, and most of the regulators are powered off. logic states in the digital core are saved and preserved into a retent ion memory in the always-on domain before the digital core is p owered off. upon a wake-up event triggered by th e pmu timers, an external interrupt, or a ho st resume through the sdio bus, logic stat es in the digital core are restored to their pre-deep-sleep settings to avoid lengthy hw reinitialization. power-down mode?the cyw88335 is effectively powered off by shutti ng down all internal regulators. the chip is brought out of this mode by external logic reenabling the internal regulators. 2.4 pmu sequencing the pmu sequencer is responsible for minimizing system power consumption. it enables and disables various system resources based on a computation of the required resources and a table that describes the relationship between resources and the time nee ded to enable and disable them. resource requests may come from several sources: clock requests from cores, the minimum resources defined in the resourcemin register, and the resources requested by any active resource re quest timers. the pmu sequencer maps clock requests into a set o f resources required to pro duce the requested clocks. each resource is in one of four states (enabled, disabled, transition_on, and transiti on_off) and has a timer that contains 0 w hen the resource is enabled or disabled and a nonzero value in the tr ansition states. the timer is loaded with the time_on or time_off value of the resource when the pmu determines that t he resource must be enabled or disabled. that timer decrements on each 32.768 khz pmu clock. when it reaches 0, the state changes from transition_off to disabled or tr ansition_on to enabled. if the time_on val ue is 0, the resource can go immediately from disabled to enabled. sim ilarly, a time_off value of 0 indicates that the resource can g o immediately from enabled to disabled. the terms enable sequence an d disable sequence refer to either the immediate transition o r the timer load-decrement sequence. during each clock cycle, t he pmu sequencer performs the following actions: computes the required resource set based on requests and the resource dependency table. decrements all timers whose values are non zero. if a timer re aches 0, the pmu clears the reso urcepending bit for the resource and inverts the resourcestate bit. compares the request with the current resource status and determines which re sources must be enabled or disabled. initiates a disable sequence for each resource that is enabl ed, no longer being requested, and has no powered up dependents. initiates an enable sequence for each resource that is disabled , is being requested, and has all of its dependencies enabled.
document number: 002-15057 rev. *b page 11 of 110 cyw88335 2.5 power-off shutdown the cyw88335 provides a low-power shutdown feature that allows the device to be tu rned off while the host, and any other device s in the system, remain operational. when the cyw88335 is not needed in the system, vddio_rf and vddc are shut down while vddio remains powered. this allows the cyw88335 to be effectively off while keeping the i/o pins powered so that they do not dr aw extra current from any other devices connected to the i/o. during a low-power shut-down state, the provided vddio remains a pplied to the cyw88335, all outputs are tristated, and most inp ut signals are disabled. input volta ges must remain within the limits defined for norma l operation. this is done to prevent curren t paths or create loading on any digital signals in the system, and enable s the cyw88335 to be fully integrated in an embedded device a nd take full advantage of the lowest power-savings modes. when the cyw88335 is powered on from this state, it is the same as a normal powe r-up, and the device does not retain any information about its state from before it was powered down. 2.6 power-up/power -down/reset circuits the cyw88335 has two signals (see ta b l e 2 ) that enable or disable the bluetooth and wlan circuits and the internal regulator blocks, allowing the host to control power consumption. for timing diagra ms of these signals and the required power-up sequences, see power-up sequence and timing on page 102 . table 2. power-up/power-down/reset control signals signal description wl_reg_on this signal is used by the pmu (with bt_reg_on) to pow er up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw88335 regulato rs. when this pin is high, the regulators are enabled and the wlan section is out of reset. when this pin is low, the wlan section is in reset. if bt_reg_on and wl_reg_on are both low, the regulators ar e disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. bt_reg_on this signal is used by the pmu (with wl_reg_on) to decide whether or not to power down the internal cyw88335 regulators. if bt_reg_on and wl_reg_on are lo w, the regulators will be disabled. this pin has an internal 200 k ? pull-down resistor that is enabled by de fault. it can be disabled through programming.
document number: 002-15057 rev. *b page 12 of 110 cyw88335 3. frequency references an external crystal is used for generating all radio frequencies and normal operation clocking. as an alternative, an external frequency reference may be used. in addition, a low-power oscillator (lpo) is provided for lower power mode timing. 3.1 crystal interface and clock generation the cyw88335 can use an external crystal to provide a frequency reference. the reco mmended configuration for the crystal oscill ator, including all external components, is shown in figure 4 . consult the reference schematics for the latest configuration and recom- mended components. figure 4. recommended oscillator configuration a fractional-n synthesizer in the cyw883 35 generates the radio frequencies, clocks, and data/packet timing, enabling the cyw883 35 to operate using a wide selection of frequency references. for sdio applications, the recommended defau lt frequency reference is a 37.4 mhz cryst al. the signal characteristics for the cr ystal interface are listed in table 3 on page 13 . note: although the fractional-n synthesizer can support alternative re ference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. contact cypress for details. 3.2 external frequency reference as an alternative to a crystal, an external precision freque ncy reference can be used. the recommended default frequency is 37. 4 mhz. this must meet the phas e noise requirements listed in ta b l e 3 . if used, the external clock should be connected to the wrf_xta l_in pin through an external 1000 pf coupling capacitor, as shown in figure 5 . the internal clock buffer connected to this pin will be tu rned off when the cyw88335 goes into sleep mode. when the clock buffer turns on and off, there will be a small impedance variation. power must be supplied to the wrf_xtal_buck_vdd1p5 pin. figure 5. recommended ci rcuit to use with an external reference clock wrf_xtal_out wrf_xtal_in c ? * c ? * x ? ohms ? * * values ? determined ? by ? crystal ? drive level. ? see ? reference ? schematics ? for ? details. ? 37.4 ? mhz reference ? clock nc 1000 ? pf wrf_xtal_in wrf_xtal_out
document number: 002-15057 rev. *b page 13 of 110 cyw88335 table 3. crystal oscillator and external clock?requirements and performance parameter conditions/notes crystal a a. (crystal) use wrf_xtal_in and wrf_xtal_out. external frequency reference b c b. see ?external frequency reference? on page 12 for alternative connection methods. c. for a clock reference other than 37.4 mhz, 20 log10(f/37.4) db should be added to the limits, where f = the reference clock frequency in mhz. min. typ. max. min. typ. max. units frequency 2.4 ghz and 5 ghz bands, ieee 802.11ac operation 35 37.4 38.4 ? 37.4 ? mhz frequency 5 ghz band, ieee 802.11n operation only 19 37.4 38.4 35 37.4 38.4 mhz frequency 2.4 ghz band ieee 802.11n operation, and both bands legacy 802.11a/b/g operation only ranges between 19 mhz and 38.4 mhz d d. the frequency step size is approximately 80 hz. frequency tolerance over the lifetime of the equipment, including temperature e e. it is the responsibility of the equipment designer to select oscillator components that comp ly with these specifications. without trimming ?20 ? 20 ?20 ? 20 ppm crystal load capacitance ? ? 12 ? ? ? ? pf esr ? ? ?60? ? ? ? drive level external crystal must be able to tolerate this drive level. 200????? w input impedance (wrf_xtal_in) resistive ? ? ? 30k 100k ? ? capacitive ? ? 7.5 ? ? 7.5 pf wrf_xtal_in input low level dc-coupled digital signal ? ? ? 0 ? 0.2 v wrf_xtal_in input high level dc-coupled digital signal ? ? ? 1.0 ? 1.26 v wrf_xtal_in input voltage (see figure 5 ) ac-coupled analog signal ? ? ? 1000 ? 1200 mv p-p duty cycle 37.4 mhz clock ? ? ? 40 50 60 % phase noise f (ieee 802.11b/g) f. assumes that external clock has a fl at phase-noise response above 100 khz. 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?129 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?136 dbc/hz phase noise f (ieee 802.11a) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?137 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?144 dbc/hz phase noise f (ieee 802.11n, 2.4 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?134 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?141 dbc/hz phase noise f (ieee 802.11n, 5 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?142 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?149 dbc/hz phase noise f (ieee 802.11ac, 5 ghz) 37.4 mhz clock at 10 khz offset ? ? ? ? ? ?148 dbc/hz 37.4 mhz clock at 100 khz offset ? ? ? ? ? ?155 dbc/hz
document number: 002-15057 rev. *b page 14 of 110 cyw88335 3.3 frequency selection any frequency within the ranges specified for the crystal and tc xo reference may be used. thes e include not only the standard mobile platform reference frequencies of 19.2, 19.8, 24, 26, 33.6, 37.4, and 38.4 mhz, but also other frequencies in this range with an approximate resolution of 80 hz. the cyw88335 must have the reference frequency set correctly in order for any of the uart o r pcm interfaces to function correctly, since all bi t timing is derived from the reference frequency. note: the fractional-n synthesizer can support many reference freq uencies. however, frequencies other than the default require support to be added in the driver plus additional, extensive system testing. contact cypress for details. the reference frequency for the cyw88335 may be set in the following ways: set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency. autodetect any of the standard handset reference frequencies using an external lpo clock. for applications where the reference freque ncy is one of the standard frequencies commonly used, the cyw88335 automatically detects the reference frequency and programs itself to the corre ct reference frequency. in or der for automatic frequency detect ion to work correctly, the cyw88335 must have a valid and stable 32 .768 khz lpo clock that meets the requirements listed in table 4 on page 14 and is present during power-on reset. 3.4 external 32.768 khz low-power oscillator the cyw88335 uses a secondary low-frequency clock for low-powe r-mode timing. an external 32.768 khz precision oscillator is required. use a precision external 32.768 khz clock that meets the requirements listed in table 4 . table 4. external 32.768 kh z sleep clock specifications parameter lpo clock units nominal input frequency 32.768 khz frequency accuracy 200 ppm duty cycle 30?70 % input signal amplitude 200?1800 mv, p-p signal type square-wave or sine-wave ? input impedance a a. when power is applied or switched off. >100k <5 ? pf clock jitter (during in itial start-up) <10,000 ppm
document number: 002-15057 rev. *b page 15 of 110 cyw88335 4. bluetooth s ubsystem overview the cypress cyw88335 is a bluetooth 4.1 + edr-compliant, baseband processor/2.4 ghz tr ansceiver. it features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power cons umption, and system co st of a bluetooth solution. the cyw88335 is the op timal solution for any bl uetooth voice and /or data application. the bluetooth subsyst em presents a standa rd host controller interface (hci) via a high-speed uart and pcm for audio. the cyw88335 incorporates all bluetooth 4.1 features including secure simple pairing, sniff subrating, and encryption pause and resume. the cyw88335 bluetooth radio transceiver pr ovides enhanced radio performance to meet automotive grade 3 temperature appli- cations and the tightest integration into aut omotive platforms. it is fully compatible with any of the standard tcxo frequencie s and provides full radio compatibility to operate si multaneously with gps, wlan, and cellular radios. the bluetooth transmitter also features a cla ss 1 power amplifier with class 2 capability. 4.1 features major bluetooth features of the cyw88335 include: supports key features of upcoming bluetooth standards fully supports bluetooth core specification vers ion 4.1 + (enhanced data rate) edr features: ? adaptive frequency hopping (afh) ? quality of service (qos) ? extended synchronous connections (esco)?voice connections ? fast connect (interlaced page and inquiry scans) ? secure simple pairing (ssp) ? sniff subrating (ssr) ? encryption pause resume (epr) ? extended inquiry response (eir) ? link supervision timeout (lst) uart baud rates up to 4 mbps supports bluetooth 4.1 fo r automotive applications supports maximum bluetooth data rates over hci uart multipoint operation with up to seven active slaves ? maximum of seven simultaneous active acl links ? maximum of three simultaneous active sco and esco connections with scatternet support trigger broadcom fast connect (tbfc) narrowband and wideband packet loss concealment scatternet operation with up to four active pico nets with background scan and support for scatter mode high-speed hci uart transport suppo rt with low-power out-of-band bt_dev_ wake and bt_host_wake signaling (see host controller power management on page 19 ) channel quality driven data rate and packet type selection standard bluetooth test modes extended radio and production test mode features full support for po wer savings modes ? bluetooth clock request ? bluetooth standard sniff ? deep-sleep modes and software regulator shutdown tcxo input and autodetection of all stand ard handset clock frequencies. also supports a low-power crystal, which can be used during power save mode for better timing accuracy.
document number: 002-15057 rev. *b page 16 of 110 cyw88335 4.2 bluetooth radio the cyw88335 has an integrated radio transce iver that has been optimized for use in 2.4 ghz bluetoot h wireless systems. it has been designed to provide low-power, low-cost, robust communicati ons for applications operating in the globally available 2.4 gh z unlicensed ism band. it is fully compliant with the bluetooth radio specification and edr specification and meets or exceeds th e requirements to provide the highest communication link quality. 4.2.1 transmitter the cyw88335 features a fully integrated ze ro-if transmitter. the baseband transmit da ta is gfsk-modulated in the modem block and upconverted to the 2.4 ghz ism band in the transmitter path. t he transmitter path performs signal filtering, i/q upconversi on, output power amplification, and rf filtering. the transmitt er path also incorporates ? /4-dqpsk and 8-dpsk modulations for 2 mbps and 3 mbps edr support, respectively. the transmitter section is comp atible to the bluetooth low e nergy specification. the trans - mitter pa bias can also be adjusted to provide bluetooth class 1 or class 2 operation. digital modulator the digital modulator performs the data modu lation and filtering required for the gfsk, ? /4-dqpsk, and 8-dpsk signal. the fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the trans- mitted signal and is much more stable than direct vco modulation schemes. digital demodulator an d bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit- synchronization algorithm. power amplifier the fully integrated pa supports class 1 or class 2 output using a highly linearized, temperature-compensated design. this prov ides greater flexibility in front-end matching and filtering. due to th e linear nature of the pa combi ned with some integrated filte ring, external filtering is required to meet the bluetooth and regulatory harmonic and spur ious requirements. for integrated telematics applic ations in which bluetooth is integrated next to the cellular radio, external filtering ca n be applied to achieve near-thermal-noise le vels for spurious and radiated noise emissions. t he transmitter features a sophisticated on-ch ip transmit signal strength indicator (tss i) block to keep the absolute output power variation within a tight range across proces s, voltage, and temperature. 4.2.2 receiver the receiver path uses a low-if scheme to downconvert the rece ived signal for demodulation in the digital demodulator and bit synchronizer. the receiver path provides a high degree of linear ity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz is m band. the front-end topology, with built-in out-of-band attenua tion, enables the cyw88335 to be used in most applications with minima l off-chip filtering. for integrated telematics operation, in w hich the bluetooth function is integrated close to the cellular transmitter, exte rnal filtering is require d to eliminate the desensi tization of the receiver by the cellular transmit signal. digital demodulator and bit synchronizer the digital demodulator and bit synchronizer take the low-if received signal and perform an optimal frequency tracking and bit synchronization algorithm. receiver signal strength indicator the radio portion of the cyw88335 provides a receiver signal strength indicator (rssi) signal to the baseband, so that the cont roller can determine whether the transmitter should increase or decrease its output power. local oscillator generation local oscillator (lo) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. the lo generation subblock employs an architecture for high immu nity to lo pulling during pa operation. the cyw88335 uses an internal rf and if loop filter. calibration the cyw88335 radio transceiver features an automated calibration sch eme that is fully self contained in the radio. no user inte raction is required during normal operation or during manufacturing to provide the optimal performance. calibration optimizes the perfo r- mance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. this take s into account process variation and temperature variation. calibration occurs during normal operation during the settling time of the hops and calibrates for temperature variations as th e device cools and heats during normal o peration in its environment.
document number: 002-15057 rev. *b page 17 of 110 cyw88335 5. bluetooth baseband core the bluetooth baseband core (bbc) implements all of the time cr itical functions required for hi gh-performance bluetooth operati on. the bbc manages the buffering, segmentation, and routing of dat a for all connections. it also buffers data that passes through it, handles data flow control, schedul es sco/acl tx/rx transactions, monitors blueto oth slot usage, optimal ly segments and packages data into baseband packets, manages connection status indicators , and composes and decodes hci packets. in addition to these functions, it independently handles hci event types, and hci command types. the following transmit and receive functions are also implemented in the bbc hardware to increase reliability and security of t he tx/ rx data: symbol timing recovery, data deframing, forward error correction (fec), header error control (hec), cyclic redundancy check (cr c), data decryption, and data dewhi tening in the receiver. data framing, fec generation, hec generati on, crc generation, key generation, data encryption, and data whitening in the transmitter. 5.1 bluetooth 4.1 features the bbc supports all bluetooth 4.1 fe atures, with the following benefits: dual-mode bluetooth low energy (bt and ble operation) extended inquiry response (eir): shortens the time to re trieve the device name, specif ic profile, and operating mode. encryption pause resume (epr): enables the use of blue tooth technology in a much more secure environment. sniff subrating (ssr): optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. secure simple pairing (ssp): reduces the number of steps for connecting two devices, with minima l or no user interaction requir ed. link supervision time out (lsto): additional commands added to hci and link management prot ocol (lmp) for improved link time-out supervision. qos enhancements: changes to data traffic cont rol, which results in better link performa nce. audio, human interface device (hid ), bulk traffic, sco, and enhanced sco (esco) are improved with th e erroneous data (ed) and packet boundary flag (pbf) enhance- ments. 5.2 bluetooth low energy the cyw88335 supports the bluetooth low energy operating mode. 5.3 link control layer the link control layer is part of the bluetooth link control func tions that are implemented in dedicated logic in the link cont rol unit (lcu). this layer consists of the command contro ller that takes commands from the software, and other controllers that are activated o r configured by the command controller to perform the link co ntrol tasks. each task performs a di fferent state in the bluetooth l ink controller. major states: ? standby ? connection substates: ? page ? page scan ? inquiry ? inquiry scan ? sniff
document number: 002-15057 rev. *b page 18 of 110 cyw88335 5.4 test mode support the cyw88335 fully supports bluetooth test mode as described in part i:1 of the specification of the blue tooth system version 3.0 . this includes the transmitter tests, normal and del ayed loopback tests, and reduced hopping sequence. in addition to the standard bluetooth test m ode, the cyw88335 also supports enhanced te sting features to simplify rf debugging, qualification, and type-approval testing. these features include: fixed-frequency carrier-wave (unmodulated) transmission ? simplifies some type-approval measurements (japan) ? aids in transmitter performance analysis fixed-frequency constant-receiver mode ? receiver output directed to i/o pin ? allows for direct ber measurements using standard rf test equipment ? facilitates spurious emissi ons testing for receive mode fixed frequency constant transmission ? eight-bit fixed pattern or prbs-9 ? enables modulated signal measurements with standard rf test equipment 5.5 bluetooth power management unit the bluetooth power management unit (pmu) pr ovides power management features that can be invoked by either software through power management registers or packet handling in the baseband co re. the power management functions provided by the cyw88335 are: rf power management host controller power management bbc power management on page 21 5.5.1 rf power management the bbc generates power-down control signals to the 2.4 ghz tran sceiver for the transmit path, receive path, pll, and power amplifier. the transceiver then processes the power-down functions accordingly.
document number: 002-15057 rev. *b page 19 of 110 cyw88335 5.5.2 host controller power management when running in uart mode, the cyw88335 may be configured so that dedicated signals are used for power management handshaking between the cyw88335 and the host. the basic power sa ving functions supported by t hose handshaking signals include the standard bluetooth defined power savi ngs modes and standby modes of operation. ta b l e 5 describes the power-control handshake signals used with the uart interface. table 5. power control pin description signal mapped to pin type description bt_dev_wake bt_gpio_0 i bluetooth device wake-up: signal fr om the host to the cyw88335 indicating that the host requires attention. asserted: the bluetooth device must wake-up or remain awake. deasserted: the bluetooth device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. bt_host_wake bt_gpio_1 o host wake up. signal from the cyw88335 to the host indicating that the cyw88335 requires attention. asserted: host device must wake-up or remain awake. deasserted: host device may sleep when sleep criteria are met. the polarity of this signal is software configurable and can be asserted high or low. clk_req bt_clk_req_out wl_clk_req_out o the cyw88335 asserts clk_req when either the bluetooth or wlan block wants the host to turn on the reference clock. the clk_req polarity is active-high. add an external 100 k ? pull-down resistor to ensure the signal is deasserted when the cyw88335 powers up or resets when vddio is present. note: pad function control register is set to 0 for these pins. see dc characteristics on page 65 for more details.
document number: 002-15057 rev. *b page 20 of 110 cyw88335 figure 6. startup signaling sequence hostresetx vddio lpo bt_gpio_0 (bt_dev_wake) bt_uart_cts_n clk_req_out bt_gpio_1 (bt_host_wake) bt_reg_on bt_uart_rts_n host ios configured host ios unconfigured bth ios configured bth ios unconfigured t 4 t 5 t 3 t 2 t 1 notes : t 1 is the time for the host to settle its ios after a reset. t 2 is the time for the host to drive bt_reg_on high after the host ios are configured. t 3 is the time for the bth device to settle its ios after a reset and the reference clock settling time has elapsed. t 4 is the time for the bth device to drive bt_uart_rts_n low after the host drives bt_uart_cts_n low. this assumes the bth device has completed initialization. t 5 is the time for the bth device to drive clk_req_out high after bt_reg_on goes high. the clk_req_out pin is used in designs that have an external reference clock source from the host. it is irrelevant on clock-based designs where the bth device generates its own reference clock from an external crystal connected to its oscillator circuit. the timing diagram assumes that vbat is present. driven pulled host drives this low. bth device drives this low indicating transport is ready.
document number: 002-15057 rev. *b page 21 of 110 cyw88335 5.5.3 bbc power management the following are low-power operations for the bbc: physical layer packet-handling turns the rf on and off dynamically within transmit/receive packets. bluetooth-specified low-power connection mode s: sniff, hold, and park. while in thes e modes, the cyw88335 runs on the low-power oscillator and wakes up after a predefined time period. a low-power shutdown feature a llows the device to be turned off while the host and any other devices in the system remain opera tional. when the cyw88335 is not needed in the system, the rf and core supplies are shut down while the i/o remains powered. this allows the cyw88335 to effectively be off while keeping the i/o pins powered so they do not draw extra curr ent from any other devices connected to the i/o. during the low-power shut-down state, pr ovided vddio remains applied to the cyw88335 , all outputs are tristated, and most input signals are disabled. input voltages must remain within the limit s defined for normal operation. this is done to prevent curren t paths or create loading on any digital signals in the system and enables the cyw88335 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. two cyw88335 input signals are designed to be high-impedance inputs that do not load the driving si gnal even if the chip does n ot have vddio power supplied to it: the frequency reference inpu t (wrf_tcxo_in) and the 32.768 khz input (lpo). when the cyw88335 is powered on from th is state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. 5.5.4 wideband speech the cyw88335 provides support for wideband speech (wbs) us ing on-chip smartaudio technology. the cyw88335 can perform subband-codec (sbc), as well as msbc, encoding and decoding of lin ear 16 bits at 16 khz (256 kbps rate) transferred over the pcm bus. 5.5.5 packet loss concealment packet loss concealment (plc) improves apparent audio quality fo r systems with marginal link performance. bluetooth messages are sent in packets. when a packet is lost, it creates a gap in the received audio bitstream. packet loss can be mitigated in s everal ways: fill in zeros. ramp down the output audio signal toward zero (thi s is the method used in current bluetoot h headsets). repeat the last frame (or packet) of the receiv ed bitstream and decode it as usual (frame repeat). these techniques cause distortion and popping in the audio stre am. the cyw88335 uses a proprietary waveform extension algorithm to provide dramatic improvem ent in the audio quality. figure 7 and figure 8 show audio waveforms with and without packet loss concealment. cypress plc and bit-error correction (bec) algorithms also support wideband speech. figure 7. cvsd decoder output waveform without plc packet loss causes ramp-down
document number: 002-15057 rev. *b page 22 of 110 cyw88335 figure 8. cvsd decoder output waveform after applying plc 5.5.6 audio rate-matching algorithms the cyw88335 has an enhanced rate-matching algorithm that uses in terpolation algorithms to reduc e audio stream jitter that may be present when the rate of audio data coming from the host is not the same as t he bluetooth audio data rates. 5.5.7 codec encoding the cyw88335 can support sbc and msbc encoding and decoding for wideband speech. 5.5.8 multiple simultaneo us a2dp audio streams the cyw88335 has the ability to take a single audio stream and ou tput it to multiple bluetooth devices simultaneously. this all ows a user to share his or her music (or any audio stream) with a friend. 5.6 adaptive frequency hopping the cyw88335 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. the link quality is determined using both rf and base band signal processing to provide a more accurate frequency-hop map. 5.7 advanced bluetooth/wlan coexistence the cyw88335 includes advanced coexistence technologies that are only possible with a bluetooth/wlan integrated die solution. these coexistence technologies are targeted at small form-factor platforms, such as infotainment and telematics modules, includ ing applications such as vowlan + sco and video-over-wlan + high fidelity bt stereo. support is provided for platforms that share a single antenna between bluetooth and wlan. the cy w88335 radio architecture allow s for lossless simultaneous bluetooth and wlan reception for shared antenna applications. this is possible only via an integrated solution (shared lna and joint agc algorithm). it has superior perf ormance versus implementations that need to arbitrate betwee n bluetooth and wlan reception. the cyw88335 integrated solution enables mac-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. information is exchanged between the bluetooth and wlan cores without host processor involvement. the cyw88335 also supports transmit power control (tpc) on th e sta together with standard bl uetooth tpc to limit mutual interference and receiver desensitization. preemption mechanisms are utilized to prevent ap transmissions from colliding with bluetooth frames. improved channel classification techniques hav e been implemented in bluetooth for faster and more accurate detection and elimination of interferers (including non-wlan 2.4 ghz interference). the bluetooth afh classification is also enhanced by the wlan core?s channel information. 5.8 fast connection (interlaced page and inquiry scans) the cyw88335 supports page scan and inquiry scan modes that sign ificantly reduce the average inquiry response and connection times. these scanning modes are compatible with the bluetooth version 2.1 page and inquiry procedures.
document number: 002-15057 rev. *b page 23 of 110 cyw88335 6. microprocessor and memory unit for bluetooth 6.1 overview the bluetooth microprocessor core is based on the arm ? cortex-m3 ? 32-bit risc processor with embedded ice-rt debug and jtag interface units. it runs software from the link cont rol (lc) layer, up to the host controller interface (hci). the arm core is paired with a memory unit that contains 608 kb of rom memory for program stor age and boot rom, 192 kb of ram for data scratch-pad and patch ram code. the internal rom a llows for flexibility during power-on reset to enable the same device to be used in various configurations. at power-up, the lo wer-layer protocol stack is exec uted from the internal rom memo ry. external patches may be applied to the rom-based firmware to pr ovide flexibility for bug fixes or feature additions. these patc hes may be downloaded from the host to the cyw88335 through the uart transports. 6.2 ram, rom, and patch memory the cyw88335 bluetooth core has 192 kb of internal ram whic h is mapped between general pu rpose scratch-pad memory and patch memory and 608 kb of rom used for t he lower-layer protocol stack, test mode software, and boot rom. the patch memory capability enables feature additions and bug fixes to the rom memory. 6.3 reset the cyw88335 has an integrated power-on reset circuit that resets all circuits to a known power-on state. the bt power-on reset (por) circuit is out of reset after bt_reg_on goes high. if bt_reg_on is low, then the por circuit is held in reset.
document number: 002-15057 rev. *b page 24 of 110 cyw88335 7. bluetooth periph eral transport unit 7.1 pcm interface the cyw88335 supports two independent pcm in terfaces that shar e pins with the i 2 s interfaces. the pcm interface on the cyw88335 can connect to linear pcm codec devices in master or slave mode. in master mo de, the cyw88335 generates the pcm_clk and pcm_sync signals, and in slave mode, these signal s are provided by another master on the pcm interface and are inputs to the cyw88335. the configuration of the pcm interface may be adjusted by the host through the use of vendor-specific hci commands. 7.1.1 slot mapping the cyw88335 supports up to three simultaneous full-duplex sco or esco channels through the pcm interface. these three channels are time-multiplexed onto the single pcm interface by us ing a time-slotting scheme where the 8 khz or 16 khz audio sam ple interval is divided into as many as 16 slots. the number of slots is dependent on the selected in terface rate of 128 khz, 512 k hz, or 1024 khz. the corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. transmit and receive pcm data from an sco channel is always mapped to the same slot. t he pcm data output driver tristate s its output on unused slots to allow other devices to share the same pcm interface signals. the data output driver tristates its ou tput after the falling edge of th e pcm clock during the last bit of the slot. 7.1.2 frame synchronization the cyw88335 supports both short- and long- frame synchronization in both master and slave modes. in short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. the pcm slave looks for a high on the falling edge of the bit clock and expec ts the first bit of the first slot to start at th e next rising edge of the cl ock. in long-frame synchroni zation mode, the frame synchr onization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts c oincident with the first bit of the first slot. 7.1.3 data formatting the cyw88335 may be configured to generate and accept several different data formats. for conventional narrowband speech mode, the cyw88335 uses 13 of the 16 bits in each pcm frame. the location and order of thes e 13 bits can be configured to support var ious data formats on the pcm interface. the remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. the default format is 13-bit 2? s complement data, left justified, and clocked msb first. 7.1.4 wideband speech support when the host encodes wideband speech (wbs) packets in transpa rent mode, the encoded packets are transferred over the pcm bus for an esco voice connection. in this mode, the pcm bus is ty pically configured in master m ode for a 4 khz sync rate with 1 6- bit samples, resulting in a 64 kbps bit rate. the cyw88335 also supports slave transparent mode using a proprietary rate-matchi ng scheme. in sbc-code mode, linear 16-bit data at 16 kh z (256 kbps rate) is transferred over the pcm bus.
document number: 002-15057 rev. *b page 25 of 110 cyw88335 7.1.5 multiplexed bluetooth over pcm to support multiple bluetooth audio stream s within the bluetooth channel, both 16 khz and 8 khz streams can be multiplexed. thi s mode of operation is only supported when the bluetooth ho st is the master. figure 9 shows the operation of the multiplexed transport with three simultaneous sco connections. to accommodate additi onal sco channels, the transport clock speed is increased. to change between modes of operation, the transport must be halted and restarted in the new configuration. figure 9. functional multiplex data diagram pcm_sync pcm_in pcm_out fm right fm left fm right fm left bt sco 1 tx bt sco 2 tx bt sco 3 tx bt sco 1 rx bt sco 2 rx bt sco 3 rx 1 frame pcm_clk 16 bits per sco frame clk 16 bits per frame 16 bits per frame each sco channel duplicates the data 6 times. each wbs frame duplicates the data 3 times per frame
document number: 002-15057 rev. *b page 26 of 110 cyw88335 7.1.6 pcm interface timing short frame sync, master mode figure 10. pcm timing diagram (short frame sync, master mode) table 6. pcm interface timing specifications (short frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7
document number: 002-15057 rev. *b page 27 of 110 cyw88335 short frame sync, slave mode figure 11. pcm timing diagram (short frame sync, slave mode) table 7. pcm interface timing specifications (short frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8
document number: 002-15057 rev. *b page 28 of 110 cyw88335 long frame sync, master mode figure 12. pcm timing diagram (long frame sync, master mode) table 8. pcm interface timing specifications (long frame sync, master mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync delay 0 ? 25 ns 5 pcm_out delay 0 ? 25 ns 6 pcm_in setup 8 ? ? ns 7 pcm_in hold 8 ? ? ns 8 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0?25ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 pcm_in 6 8 high ? impedance 7 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-15057 rev. *b page 29 of 110 cyw88335 long frame sync, slave mode figure 13. pcm timing diagram (long frame sync, slave mode) table 9. pcm interface timing specifications (long frame sync, slave mode) ref no. characteristics minimum typical maximum unit 1 pcm bit clock frequency ? ? 12 mhz 2 pcm bit clock low 41 ? ? ns 3 pcm bit clock high 41 ? ? ns 4 pcm_sync setup 8 ? ? ns 5 pcm_sync hold 8 ? ? ns 6 pcm_out delay 0 ? 25 ns 7 pcm_in setup 8 ? ? ns 8 pcm_in hold 8 ? ? ns 9 delay from rising edge of pcm_bclk during last bit period to pcm_out becoming high impedance 0 ? 25 ns pcm_bclk pcm_sync pcm_out 1 2 3 4 5 6 pcm_in 7 9 high ? impedance 8 bit ? 0 bit ? 0 bit ? 1 bit ? 1
document number: 002-15057 rev. *b page 30 of 110 cyw88335 7.2 uart interface the uart is a standard 4-wire interface (rx, tx, rts, and cts) with adjustable baud rates from 9600 bps to 4.0 mbps. the interf ace features an automatic baud rate detection capability that return s a baud rate selection. alternatively, the baud rate may be se lected through a vendor-specific uart hci command. uart has a 1040-byte receive fifo and a 1040-byte transmit fifo to support edr. access to the fifos is conducted through the ahb interface through either dma or the cpu. the uart supports the bluetooth 4.1 uart hci specification: h4, a custom extended h4, and h5. the default baud rate is 115.2 kbaud. the uart supports the 3-wire h5 uart transport, as described in the bluetooth specific ation (?three-wire uart transport layer?) . compared to h4, the h5 uart transport reduces the number of signal lines required by eliminating the cts and rts signals. the cyw88335 uart can perform xon/xoff flow control and includes hardware support for the serial line input protocol (slip). it can also perform wake-on activi ty. for example, activity on the rx or cts inputs can wake the chip from a sleep state. normally, the uart baud rate is set by a configuration record downloaded after device reset, or by automatic baud rate detectio n, and the host does not need to adjust the baud rate. support for changing the baud rate during normal hci uart operation is incl uded through a vendor-specific command that allo ws the host to adjust the contents of t he baud rate registers. the cyw88335 uarts operate correctly with the host uart as long as the co mbined baud rate error of the two devices is within 2%. table 10. example of common baud rates desired rate actual rate error (%) 4000000 4000000 0.00 3692000 3692308 0.01 3000000 3000000 0.00 2000000 2000000 0.00 1500000 1500000 0.00 1444444 1454544 0.70 921600 923077 0.16 460800 461538 0.16 230400 230796 0.17 115200 115385 0.16 57600 57692 0.16 38400 38400 0.00 28800 28846 0.16 19200 19200 0.00 14400 14423 0.16 9600 9600 0.00
document number: 002-15057 rev. *b page 31 of 110 cyw88335 figure 14. uart timing 7.3 i 2 s interface the cyw88335 supports two independent i 2 s digital audio ports. the i 2 s signals are: i 2 s clock: i 2 s sck i 2 s word select: i 2 s ws i 2 s data out: i 2 s sdo i 2 s data in: i 2 s sdi i 2 s sck and i 2 s ws become outputs in master mode and inputs in slave mode, while i 2 s sdo always stays as an output. the channel word length is 16 bits and the data is justified so that the msb of the left-channel data is aligned with the msb of the i 2 s bus, per the i 2 s specification. the m sb of each data word is transmitt ed one bit clock cycle after the i 2 s ws transition, synchronous with the falling edge of bit clock. left-channel data is transmitted when i 2 s ws is low, and right-channel data is transmitted when i 2 s ws is high. data bits sent by the cyw88335 are synchronized with the falli ng edge of i2s_sck and should be sampled by the receiver on the rising edge of i2s_ssck. the clock rate in master mode is either of the following: 48 khz x 32 bits per frame = 1.536 mhz 48 khz x 50 bits per frame = 2.400 mhz the master clock is generated from the inpu t reference clock using a n/m clock divider. in the slave mode, any clock rate is supported to a maximum of 3.072 mhz. table 11. uart timing specifications ref no. characteristics min. typ. max. unit 1 delay time, uart_cts_n low to uart_txd valid ? ? 1.5 bit period 2 setup time, uart_cts_n high before midpoint of stop bit ? ? 0.5 bit period 3 delay time, midpoint of stop bit to uart_rts_n high ? ? 0.5 bit period uart_cts_n uart_rxd uart_rts_n 1 2 midpoint ? of ? stop ? bit uart_txd 3 midpoint ? of ? stop ? bit
document number: 002-15057 rev. *b page 32 of 110 cyw88335 7.3.1 i 2 s timing note: timing values specified in table 12 are relative to high and low threshold levels. note: the time periods specified in figure 15 and figure 16 are defined by the transmitter speed. the receiver specifications must match transmitter performance. table 12. timing for i 2 s transmitters and receivers transmitter receiver notes lower limit upper limit lower limit upper limit min. max. min. max. min. max. min. max. clock period t t tr ??? t r ??? a a. the system clock period t must be greater than t tr and t r because both the transmitter and receiver have to be able to handle the data transfer rate. master mode: clock generated by transmitter or receiver high t hc 0.35t tr ??? 0.35t tr ??? b b. at all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. for thi s reason, t hc and t lc are specified with respect to t. lowt lc 0.35t tr ??? 0.35t tr ??? b slave mode: clock accepted by transmitter or receiver high t hc ? 0.35t tr ??? 0.35t tr ?? c c. in slave mode, the transmitter and receiver need a clock signal with minimum high and low periods so that they can detect the signal. so long as the minimum periods are greater than 0.35t r , any clock that meets the requirements can be used. low t lc ? 0.35t tr ??? 0.35t tr ?? c rise time t rc ?? 0.15t tr ??? ? d d. because the delay (t dtr ) and the maximum transmitter speed (defined by t tr ) are related, a fast transmitter driven by a slow clock edge can result in t dtr not exceeding t rc which means t htr becomes zero or negative. therefore, the transmitter has to guarantee that t htr is greater than or equal to zero, so long as the clock rise-time t rc is not more than t rcmax , where t rcmax is not less than 0.15t tr . transmitter delay t dtr ???0.8t???? e e. to allow data to be clocked out on a falling edge, the delay is specified with respect to th e rising edge of the clock signal and t, always giving the receiver sufficient setup time. hold time t htr 0??????? d receiver setup time t sr ????? 0.2t r ?? f f. the data setup and hold time must not be less than the specified receiver setup and hold time. hold time t hr ?????0?? f
document number: 002-15057 rev. *b page 33 of 110 cyw88335 figure 15. i 2 s transmitter timing figure 16. i 2 s receiver timing sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t rc * t hc > 0.35t t v h = ? 2.0v t htr > 0 t otr < 0.8t t ? = ? clock ? period t tr = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? = ? t tr * ? t rc is ? only ? relevant ? for ? transmitters ? in ? slave ? mode. sd ? and ? ws sck v l = ? 0.8v t lc > 0.35t t hc > 0.35 t v h = ? 2.0v t hr > 0 t sr > 0.2t t ? = ? clock ? period t r = ? minimum ? allowed ? clock ? period ? for ? transmitter t ? > ? t r
document number: 002-15057 rev. *b page 34 of 110 cyw88335 8. wlan global functions 8.1 wlan cpu and memory subsystem the cyw88335 wlan section includes an integrated arm cortex-r4 ? 32-bit processor with internal ram and rom. the arm cortex-r4 is a low-power processor that features low gate coun t, low interrupt latency, and low-cost debug capabilities. it is intended for deeply embedded applications that require fast interrupt re sponse features. delivering more than 30% performance gain over arm7tdmi, the arm cortex-r4 implements the arm v7-r architecture with support for the thumb ? -2 instruction set. at 0.19 w/mhz, the cortex-r4 is the most power efficient general-purpose microproce ssor available, outperforming 8- and 16-bit devices on mips/w. it supports integrated sleep modes. using multiple technologies to reduce cost, the arm cortex-r4 of fers improved memory utilization, reduced pin overhead, and reduced silicon area. it supports independent buses for code and data access (icode/dcode and system buses), and extensive debug features including real time trace of program execution. on-chip memory for the cpu includes 768 kb sram and 640 kb rom. 8.2 one-time programmable memory various hardware configuration parameters may be stored in an in ternal one-time programmable (otp) memory, which is read by the system software after device reset. in addition, cu stomer-specific pa rameters, including the system vendor id and the mac address can be stored, depending on the s pecific board design. customer accessible otp memory is 502 bytes. the initial state of all bits in an unprogra mmed otp device is 0. after any bit is pr ogrammed to a 1, it cannot be reprogrammed to 0. the entire otp array can be programmed in a single write cycle using a utility provided with the cypress wlan manufacturing tes t tools. alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. prior to otp memory programming, all values should be verified using the appropriate editable nv ram.txt file, which is provided with the reference board design package. otp programming is intended to be performed when the wlan /bt hardware modules are manufactured. it should not be programmed in the field or by the automobile manufacturer. addi tionally, otp programming should be done in an environment where the room temperature is between 20c and 30c. 8.3 gpio interface the following number of general-purpose i/o (gpio) pins are availa ble on the wlan section of the cyw88335 that can be used to connect to various external devices: wlbga package ? 9 gpios upon power up and reset, these pins become tris tated. subsequently, they can be programmed to be either input or output pins vi a the gpio control register. in addit ion, the gpio pins can be assigned to various other functions (see table 22 on page 61 ).
document number: 002-15057 rev. *b page 35 of 110 cyw88335 8.4 external coexistence interface an external handshake interface is available to enable signalin g between the device and an external co-located wireless device, such as gps, wimax, lte, or uwb, to manage wireless medium sharing for optimum performance. figure 17 shows the lte coexistence interface. see table 22 on page 61 for details on multiplexed signals such as the gpio pins. see table 10 on page 30 for uart baud rates. figure 17. cypress gci or bt-sig mode lte coexistence interface for the cyw88335 8.5 uart interface one 2-wire uart interface can be enabled by softw are as an alternate function on gpio pins (see table 22 on page 61 ). provided primarily for debugging during development, this uart enables the cyw88335 to operate as rs-2 32 data termination equipment (dte) for exchanging and managing data with other serial device s. it is compatible with the industry standard 16550 uart, and provides a fifo size of 64 8 in each direction. 8.6 jtag interface the cyw88335 supports the ieee 1149.1 jtag boundary scan stand ard for performing device package and pcb assembly testing during manufacturing. in addition, the jtag interface allows cy press to assist customers by using proprietary debug and charact er- ization test tools during board bring-up. therefore, it is highly recommended to provide access to the jtag pins by means of te st points or a header on all pcb designs. see table 22 on page 61 for jtag pin assignments. lte\ic wlan bt uart_in uart_out seci_out/bt_txd seci_in/bt_txd seci_out/bt_txd and seci_in/bt_rxd are multiplexed on the gpios. the 2-wire lte coexistence interface is intended for future compatibility with the bt sig 2-wire interface that is being standardized for core 4.1. oring to generate ism_rx_priority for ercx_txconf or bt_rx_priority is achieved by setting the gpio mask registers appropriately. notes: gci cyw88335
document number: 002-15057 rev. *b page 36 of 110 cyw88335 9. wlan host interfaces 9.1 sdio v3.0 the cyw88335 wlan section supports sdio ve rsion 3.0, including the new uhs-i modes: ds: default speed (ds) up to 25 mhz, including 1- and 4-bit modes (3.3v signaling). hs: high speed up to 50 mhz (3.3v signaling). sdr12: sdr up to 25 mhz (1.8v signaling). sdr25: sdr up to 50 mhz (1.8v signaling). sdr50: sdr up to 100 mhz (1.8v signaling). sdr104: sdr up to 208 mhz (1.8v signaling). ddr50: ddr up to 50 mhz (1.8v signaling). note: the cyw88335 is backward compatible with sdio v2.0 host interfaces. the sdio interface also has the ability to map the interrupt signal on to a gpio pin for applications requiring an interrupt di fferent from the one provided by the sdio interface. the ability to force control of the gated clocks from within the device is also pr ovided. sdio mode is enabled by strapping options. refer to ta b l e 1 7 wlan gpio functions and strapping options. the following three functions are supported: function 0 standard sdio function (max. blocksize/bytecount = 32b) function 1 backplane function to access the internal system -on-chip (soc) address space (max. blocksize/bytecount = 64b) function 2 wlan function for efficient wlan packet transfer through dma (max. blocksize/bytecount = 512b) 9.1.1 sdio pins figure 18. signal connections to sdio host (sd 4-bit mode) table 13. sdio pin description sd 4-bit mode sd 1-bit mode gspi mode data0 data line 0 data data line do data output data1 data line 1 or interrupt irq interrupt irq interrupt data2 data line 2 or read wait rw read wait nc not used data3 data line 3 n/c not used cs card select clk clock clk clock sclk clock cmd command line cmd command line di data input sd host clk cmd dat[3:0] cyw88335
document number: 002-15057 rev. *b page 37 of 110 cyw88335 figure 19. signal connections to sdio host (sd 1-bit mode) note: per section 6 of the sdio specif ication, pull-ups in the 10 k ? to 100 k ? range are required on the four data lines and the cmd line. this requirement must be met during all operating states either through the us e of external pull-up resistors or through proper programming of the sdio host?s internal pull-ups. 9.2 generic spi mode in addition to the full sdio mode, the cyw88335 includes the opt ion of using the simplified gene ric spi (gspi) interface/protoc ol. characteristics of the gspi mode include: supports up to 48 mhz operation supports fixed delays for responses and data from device supports alignment to host g spi frames (16 or 32 bits) supports up to 2 kb frame size per transfer supports little endian (default) and big endian configurations supports configurable active edge for shifting supports packet transfer through dma for wlan gspi mode is enabled using the strappi ng option pins stra p_host_ifc_[3:1]. figure 20. signal connections to sdio host (gspi mode) sd host clk cmd data irq rw cyw88335 sd host sclk di do irq cs cyw88335
document number: 002-15057 rev. *b page 38 of 110 cyw88335 9.2.1 spi protocol the spi protocol supports both 16-bit and 32-bit word oper ation. byte endianness is supported in both modes. figure 21 and figure 22 show the basic write and write/read commands. figure 21. gspi write protocol figure 22. gspi read protocol
document number: 002-15057 rev. *b page 39 of 110 cyw88335 command structure the gspi command structure is 32 bits. the bi t positions and definitions are as shown in figure 23 . figure 23. gspi command structure write the host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the cs going low . the following bits are clocked out on the falling edge of the gspi clock. the device samples the data on the active edge. write/read the host reads on the rising edge of the clock requiring data fr om the device to be made available before the first rising cloc k edge of the clock burst for the data. the last clock edge of the fixe d delay word can be used to represent the first bit of the foll owing data word. this allows data to be ready for the first clock edge without relying on asynchronous delays. read the read command always follows a separate write to set up the wl an device for a read. this command differs from the write/read command in the following respects: a) chip selects go high be tween the command/address and the data and b) the time interval between the command/address is not fixed. 0 10 27 11 p acket length - 11b its * ad dress C 17 bits f1 f 0 c a f unction n o: 00 C f unc 0 01 C f unc 1 10 C f unc 2 11 C f unc 3 c ommand : 0 C r ead 1 C w rite 28 29 30 31 a cce ss : 0 C f ixed add ress 1 C incremental add res s * 11 h0 = 204 8 by tes 0 10 27 11 p acket length - 11b its * ad dress C 17 bits f1 f 0 c a f unction n o: 00 C f unc woo^w/??].?p]???? 01 C f unc 1: registers and meories belonging to other blocks in the chip (64 bytes max) 10 C f unc 2: dma channel 1. wlan packets up to 2048 bytes. 11 C f unc ?wdzvvo?~}??}voxwl????}?e????x c ommand : 0 C r ead 1 C w rite 28 29 30 31 a cce ss : 0 C f ixed add ress 1 C incremental add res s * 11 h0 = 204 8 by tes bcm_spid command structure cyw
document number: 002-15057 rev. *b page 40 of 110 cyw88335 status the gspi interface supports status notification to the host after a read/write transaction. this status notificat ion provides i nformation about any packet errors, protocol errors, information about availabl e packet in the rx queue, etc. the status information helps in reducing the number of interrupts to the host. the status-reporti ng feature can be switched off us ing a register bit, without a ny timing overhead. the gspi bus timing for read/write transactions with and without status not ification are as shown in figure 24 and figure 25 on page 41 . see table 14 on page 41 for information on status field details. figure 24. gspi signal timing without status (32-bit big endian) c31 c30 c1 c0 d31 d30 d1 d0 command ? 32 ? bits write ? data ? 16*n ? bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data 16*n ? bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data ? 16*n ? bits miso cs sclk mosi response delay d1 c31 c30 c1 c0 d31 d30 d1 d0 command ? 32 ? bits write ? data ? 16*n ? bits cs sclk mosi c31 c30 c1 c0 d31 d30 d1 d0 c31 c30 c1 c0 d31 d30 d1 d0 command ? 32 ? bits write ? data ? 16*n ? bits cs sclk mosi c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data 16*n ? bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data 16*n ? bits miso cs sclk mosi response delay c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data ? 16*n ? bits miso cs sclk mosi response delay d1 c31 c30 c0 d31 d30 d0 command 32 ? bits read ? data ? 16*n ? bits miso cs sclk mosi response delay d1 write write \ read read
document number: 002-15057 rev. *b page 41 of 110 cyw88335 figure 25. gspi signal timing with status (response delay = 0; 32-bit big endian) table 14. gspi status field details bit name description 0 data not available the requeste d read data is not available 1 underflow fifo underflow occurred due to current (f2, f3) read command 2 overflow fifo overflow occurred due to current (f1, f2, f3) write command 3 f2 interrupt f2 channel interrupt 4 f3 interrupt f3 channel interrupt 5 f2 rx ready f2 fifo is ready to receive data (fifo empty) 6 f3 rx ready f3 fifo is ready to receive data (fifo empty) 7 reserved ? 8 f2 packet available packet is available/ready in f2 tx fifo 9:19 f2 packet length length of packet available in f2 fifo 20 f3 packet available packet is available/ready in f3 tx fifo 21:31 f3 packet length length of packet available in f3 fifo c31 c0 d31 d1 d0 read ? data ? 16*n ? bits miso cs sclk mosi s0 s31 status ? 32 ? bits c31 c0 d31 d1 d0 command ? 32 ? bits read ? data ? 16*n ? bits miso cs sclk mosi s0 s31 status ? 32 ? bits c31 s0 c1 c0 d31 s31 d1 d0 command ? 32 ? bits write ? data ? 16*n ? bits cs sclk mosi s1 status ? 32 ? bits miso c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 c0 d31 d1 d0 s0 s31 c31 s0 c1 c0 d31 s31 d1 d0 s1 c31 s0 c1 c0 d31 s31 d1 d0 s1 command ? 32 ? bits write write \ read read
document number: 002-15057 rev. *b page 42 of 110 cyw88335 9.2.2 gspi host-device handshake to initiate communication through the gspi after power-up, the hos t needs to bring up the wlan/chip by writing to the wake-up w lan register bit. writing a 1 to this bit will start up the necessary crystals and plls so that the cyw88335 is ready for data tran sfer. the device can signal an interrupt to the host indicating that t he device is awake and ready. this procedure also needs to be follo wed for waking up the device in sleep mode. the device can interrupt the host using the wlan irq line whenever it has any information t o pass to the host. on getting an interrupt, the host needs to read the interrupt and/or status regi ster to determine the cause o f interrupt and then take necessary actions. 9.2.3 boot-up sequence after power-up, the gspi host needs to wait 150 ms for the devi ce to be out of reset. for this, the host needs to poll with a r ead command to f0 addr 0x14. address 0x14 contai ns a predefined bit pattern. as soon as the host gets a response back with the corr ect register content, it implies that the device has powered up and is out of reset. after that, th e host needs to set the wakeup-w lan bit (f0 reg 0x00 bit 7). the wakeup-wlan issues a clock request to the pmu. for the first time after power-up, the host must wait for the availability of low power clock inside the devi ce. once that is a vailable, the host must write to a pmu register to set the crystal frequency, which turns on the p ll. after the pll is locked, the chipactive interrupt is issued to the host. this interrupt i ndicates the device awake/ready status. see ta b l e 1 5 for information on gspi registers. in table 15 , the following notation is used for register access: r: readable from host and cpu w: writable from host u: writable from cpu table 15. gspi registers address register bit access default description x0000 word length 0 r/w/u 0 0: 16 bit word length 1: 32 bit word length endianness 1 r/w/u 0 0: little endian 1: big endian high-speed mode 4 r/w/u 1 0: normal mode. rx and tx at different edges. 1: high speed mode. rx and tx on same edge (default). interrupt polarity 5 r/w/u 1 0: interrupt active polarity is low 1: interrupt active polarity is high (default) wake-up 7 r/w 0 a write of 1 will denote a wake-up command from the host to the device. this will be followed by an f2 interrupt from the gspi device to the host, indicating device awake status. x0001 response delay 7:0 r/w/u 8?h04 configurable read response delay in multiples of 8 bits x0002 status enable 0 r/w 1 0: no status sent to host after read/write 1: status sent to host after read/write interrupt with status 1 r/w 0 0: do not interrupt if status is sent 1: interrupt host even if status is sent response delay for all 2 r/w 0 0: response delay applicable to f1 read only 1: response delay applicable to all function read x0003 reserved ? ? ? ? x0004 interrupt register 0r/w0 requested data not available; cleared by writing a 1 to this location 1 r 0 f2/f3 fifo underflow due to last read 2 r 0 f2/f3 fifo overflow due to last write 5 r 0 f2 packet available 6 r 0 f3 packet available 7 r 0 f1 overflow due to last write
document number: 002-15057 rev. *b page 43 of 110 cyw88335 x0005 interrupt register 5 r 0 f1 interrupt 6 r 0 f2 interrupt 7 r 0 f3 interrupt x0006? x0007 interrupt enable register 15:0 r/w/u 16'he0e7 particular interrupt is enabled if a corresponding bit is set x0008? x000b status register 31:0 r 32'h0000 same as status bit definitions x000c? x000d f1 info register 0 r 1 f1 enabled 1 r 0 f1 ready for data transfer 13:2 r/u 12'h40 f1 max packet size x000e? x000f f2 info register 0 r/u 1 f2 enabled 1 r 0 f2 ready for data transfer 15:2 r/u 14'h800 f2 max packet size x0010? x0011 f3 info register 0 r/u 1 f3 enabled 1 r 0 f3 ready for data transfer 15:2 r/u 14'h800 f3 max packet size x0014? x0017 test?read only register 31:0 r 32'hfeed bead this register contains a predefined pattern, which the host can read and determine if the gspi interface is working properly. x0018? x001b test?r/w register 31:0 r/w/u 32'h00000 000 this is a dummy register wh ere the host can write some pattern and read it back to determine if the gspi interface is working properly. table 15. gspi registers (cont.) address register bit access default description
document number: 002-15057 rev. *b page 44 of 110 cyw88335 figure 26 shows the wlan boot-up sequence from power-up to firmware download. figure 26. wlan boot-up sequence < ? 950 ? s after ? 8 ? ms ? the ? reference ? clock ? is ? assumed ? to ? be ? up. ?? access ? to ? pll ? registers ? is ? possible. 8 ? ms ? < ? 4 ? ms ? < ? 104 ? ms ? after ? a ? fixed ? delay ? following ? internal ? por ? and ? wl_reg_on ? going ? high, ? the ? device ? responds ? to ? host ? f0 ? (address ? 0x14) ? reads. vddio wl_reg_on vddc (from ? internal ? pmu) internal ? por device ? requests ? for ? reference ? clock host ? interaction: host ? polls ? f0 ? (address ? 0x14) ? until ? it ? reads ? a ? predefined ? pattern. host ? sets ? wake \ up \ wlan ? bit ? and ? waits ? 8 ? ms, ? the ? maximum ? time ? for ? reference ? clock ? availability. after ? 8 ? ms, ? host ? programs ? pll ? registers ? to ? set ? crystal ? frequency host ? downloads ? code. chip ? active ? interrupt ? is ? asserted ? after ? the ? pll ? locks vbat* *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-15057 rev. *b page 45 of 110 cyw88335 10. wireless lan mac and phy 10.1 ieee 802.11ac mac the cyw88335 wlan mac is designed to support high-throughput operation with low-power consum ption. it does so without compromising the bluetooth coexis tence policies, thereby enabling optimal performance over both net works. in addi tion, several power saving modes have been implemented that allow the mac to consume very little power while maintaining network-wide timing synchronization. the architecture diagram of the mac is shown in figure 27 . the following sections provide an overview of the important modules in the mac. figure 27. wlan mac architecture embedded ? cpu ? interface host ? registers, ? dma ? engines tx \ fifo 32 ? kb wep tkip, ? aes, ? wapi txe tx ? a \ mpdu rxe pmq psm shared ? memory 6 ? kb psm ucode memory ext \ ihr ifs backoff, ? btcx tsf nav ihr ? bus shm ? bus mac \ phy ? interface rx \ fifo 10 ? kb rx ? a \ mpdu
document number: 002-15057 rev. *b page 46 of 110 cyw88335 the cyw88335 wlan media access controller (mac) supports feat ures specified in the ieee 802.11 base standard, and amended by ieee 802.11n. the key mac features include: enhanced mac for supporting ieee 802.11ac features transmission and reception of aggregated mpdus (a-mpdu) for high throughput (ht) support for power management schemes, including wmm power -save, power-save multi-poll (psmp) and multiphase psmp operation support for immediate ack and block-ack policies interframe space timing support, including rifs support for rts/cts and cts-to-self fram e sequences for protecting frame exchanges back-off counters in hardware for supporting multiple priorities as specified in the wmm specification timing synchronization function (tsf), network allocation vector (nav) maintenance, and target beacon transmission time (tbtt) generation in hardware hardware offload for aes-ccmp, legacy wpa tkip, legacy wep ciphers, wapi, and support for key management support for coexistence with bluetooth and other external radios programmable independent basic service set (ibss) or infrastructure basic service set functionality statistics counters for mib support psm the programmable state machine (psm) is a mi cro-coded engine, which provides most of the low-level control to the hardware, to implement the ieee 802.11 sp ecification. it is a microcontroll er that is highl y optimized for flow control operations, which ar e predom- inant in implementations of communication protocols. the inst ruction set and fundamental operations are simple and general, whi ch allows algorithms to be optimized until very late in the design process. it also allows for changes to the algorithms to track evolving ieee 802.11 specifications. the psm fetches instructions from the microc ode memory. it uses the shared memory to obtain operands for instructions, as a dat a store, and to exchange data between both th e host and the mac data pipeline (via the sh m bus). the psm also uses a scratch-pad memory (similar to a register bank) to stor e frequently accessed and temporary variables. the psm exercises fine-grained control over the hardware engines, by programming internal hardw are registers (i hr). these ihrs are co-located with the hardw are functions they control, and are a ccessed by the psm via the ihr bus. the psm fetches instructions from the micr ocode memory using an address determined by the program counter, instruction literal, or a program stack. for alu operations th e operands are obtained from shared memory , scratch-pad, ihrs, or instruction literals , and the results are written into the shared memory, scratch-pad, or ihrs. there are two basic branch instructions: cond itional branches and alu based branches. to better support the many decision point s in the ieee 802.11 algorithms, branches c an depend on either a readily available signals from the hardware modules (branch cond ition signals are available to the psm without polling the ihrs), or on the results of alu operations. wep the wired equivalent privacy (wep) engine encapsulates all the ha rdware accelerators to perform the encryption and decryption, and mic computation and verification. the accelerators implement th e following cipher al gorithms: legacy wep, wpa tkip, wpa2 aes- ccmp. the psm determines, based on the frame type and association info rmation, the appropriate cipher algorithm to be used. it suppli es the keys to the hardware engines from an on-chip key table. the wep interfaces with the txe to encrypt and compute the mic on transmit frames, and the rxe to decrypt and verify the mic on receive frames.
document number: 002-15057 rev. *b page 47 of 110 cyw88335 txe the transmit engine (txe) constitutes the transmit data path of the mac. it coordinates the dma engines to store the transmit f rames in the txfifo. it interfaces with wep module to encrypt frames , and transfers the frames acro ss the mac-phy interface at the appropriate time determined by the channel access mechanisms. the data received from the dma engines are stored in transmit fi fos. the mac supports multiple logical queues to support traffi c streams that have different qos priority requirements. the psm uses the channel access information from the ifs module to sched ule a queue from which the next frame is transmitted. once the fram e is scheduled, the txe hardware transmits the frame based on a precise timing trigger received from the ifs module. the txe module also contains the hardware t hat allows the rapid assembly of mpdus in to an a-mpdu for tr ansmission. the hardware module aggregates the encrypted mpdus by adding appropriate headers and pad delimiters as needed. rxe the receive engine (rxe) constitutes the receive data path of t he mac. it interfaces with the dma engine to drain the received frames from the rxfifo. it transfers bytes across the mac-phy interfac e and interfaces with the wep m odule to decrypt frames. the decrypted data is stored in the rxfifo. the rxe module contains programmable filters that are programmed by the psm to accept or filter frames based on several criteri a such as receiver address, b ssid, and certain frame types. the rxe module also contains the hardware required to detect a-mpdus, parse the headers of t he containers, and disaggregate them into component mpdus. ifs the ifs module contains the timers required to determine interf rame space timing including rifs timing. it also contains multip le backoff engines required to support prioritized access to the medium as specified by wmm. the interframe spacing timers are triggered by the cessation of channel activity on the medium, as indicated by the phy. these timers provide precise timing to the txe to begin frame transmission. th e txe uses this information to send response frames or perform transmit frame-bursting (rifs or sifs separated, as within a txop). the backoff engines (for each access category) monitor channel ac tivity, in each slot duration, to determine whether to continu e or pause the backoff counters. when the backoff counters reach 0, t he txe gets notified, so that it may commence frame transmissio n. in the event of multiple backoff counters decrementing to 0 at the same time, the hardware resolves the conflict based on polic ies provided by the psm. the ifs module also incorporates hardware that allows the mac to enter a low-power state when operating under the ieee power save mode. in this mode, the mac is in a suspended state with its clock turned off. a sleep time r, whose count value is initial ized by the psm, runs on a slow clock and determines the duration over which the mac remains in this suspended state. once the timer expires the mac is restored to its functi onal state. the psm updates the tsf timer based on the sleep duration ensuring that th e tsf is synchronized to the network. the ifs module also contains the pta hardware that assists the psm in bluetooth coexistence functions. tsf the timing synchronization function (tsf) module maintains th e tsf timer of the mac. it also maintains the target beacon transmission time (tbtt). the tsf timer hardware, under the cont rol of the psm, is capable of adopting timestamps received from beacon and probe response frames in order to maintain synchronization with the network. the tsf module also generates trigger signals fo r events that are specified as offsets from the tsf timer, such as uplink and d ownlink transmission times used in psmp. nav the network allocation vector (nav) timer module is responsible for maintaining the nav information conveyed through the durati on field of mac frames. this ensures that the mac complies with the protection me chanisms specified in the standard. the hardware, under the control of the psm, maintains the nav ti mer and updates the timer appropriately based on received frame s. this timing information is provided to the ifs module, which uses it as a virtual carrier-sense indication. mac-phy interface the mac-phy interface consists of a data path interface to e xchange rx/tx data from/to the phy. in addition, there is an programming interface, which can be controlled either by the host or the psm to configure and control the phy.
document number: 002-15057 rev. *b page 48 of 110 cyw88335 10.2 ieee 802.11ac phy the cyw88335 wlan digital phy is designed to comply with ieee 802.11ac and ieee 802.11a/b/g/n single-stream specifications to provide wireless lan connectivity supporting data rates from 1 mbps to 433.3 mbps for low-power, high-performance handheld applications. the phy has been designed to work in the presence of interferen ce, radio nonlinearity, and various other impairments. it incorp orates optimized implementations of the filters, fft and viterbi decoder algorithms. efficien t algorithms have been designed to achiev e maximum throughput and reliability, including algorithms for carri er sense/rejection, frequency/phase/timing acquisition and tr acking, channel estimation and tracking. the phy receiver also contains a robust ieee 802.11b demodulator. the phy carrier sense has been tuned to provide high throughput for ieee 802.11g/11b hybrid networks with bluetooth coexistence. it has also been designe d for shared single antenna systems between wl and bt to support simultaneous rx-rx. the key phy features include: programmable data rates from mcs0?9 in 20 mhz, 40 mh z, and 80 mhz channels, as specified in ieee 802.11ac supports optional short gi mode in tx and rx tx and rx ldpc for improved range and power efficiency supports optional space-time block code (stbc) receive of two space-time streams for improved throughput and range in fading channel environments. all scrambling, encoding, forward error correction, and modulati on in the transmit direction and inverse operations in the rece ive direction. supports ieee 802.11h/k for worldwide operation advanced algorithms for low power, enhanced sensitivity, range, and reliability algorithms to improve perform ance in presence of bluetooth automatic gain control scheme for blocking and non bl ocking application scenario for cellular applications closed loop transmit power control digital rf chip calibration algorithms to handle cmos rf chip non-idealities on-the-fly channel frequency and transmit power selection supports per packet rx antenna diversity available per-packet channel quality and signal strength measurements designed to meet fcc and other worldwide regulatory requirements
document number: 002-15057 rev. *b page 49 of 110 cyw88335 figure 28. wlan phy block diagram filters ? and ? radio ? comp frequency ? and ? timing ? synch carrier ? sense, ? agc, ? and ? rx ? fsm radio ? control ? block common ? logic ? block filters ? and ? radio ? comp afe ? and ? radio mac ? interface buffers ofdm ? demodulate viterbi ? decoder tx ? fsm pa ? comp modulation ? and ? coding modulate/spread frame ? and ? scramble fft/ifft cck/dsss ? demodulate descramble ? and ? deframe coex
document number: 002-15057 rev. *b page 50 of 110 cyw88335 11. wlan radio subsystem the cyw88335 includes an integrated dual-band wlan rf transce iver that has been optimized for use in 2.4 ghz and 5 ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applications operating in the globally available 2.4 ghz unlicensed ism or 5 ghz u-ni i bands. the transmit and receive sections include all on-chip fi ltering, mixing, and gain control functions. ten rf control signals are available to drive external rf swit ches and support optional external power amplifiers and low-noise amplifiers for each band. see the refere nce board schematics for further details. a block diagram of the radi o subsystem is shown in figure 29 on page 51 . note that integrated on-chi p baluns (not shown) convert the fully differential transmit and receive paths to single-ended signal pins. 11.1 receiver path the cyw88335 has a wide dynamic range, direct conversion receiver that employs high order on-chip channel filtering to ensure reliable operation in the noisy 2.4 ghz is m band or the entire 5 ghz u-nii band. an on-chip low-noise amplifier (lna) in the 2. 4 ghz path is shared between the blue tooth and wlan receivers, while the 5 ghz receiv e path has a dedicated on-chip lna. control signa ls are available that can support the use of optional lnas for each band, which can incr ease the receive sensitivity by several db . 11.2 transmit path baseband data is modulated and upconverted to the 2.4 ghz ism or 5-ghz u-nii bands, respectively. linear on-chip power amplifie rs are included, which are capable of delivering high output powers while meeting ieee 802.11ac and ieee 802.11a/b/g/n specification s without the need for external pas. when using the internal pas, closed-loop output power control is completely integrated. as a n option, external pas can be used for even higher output power, in which case the closed-loop output power control is provided b y means of a-band and g-band tssi inputs from external power detectors. 11.3 calibration the cyw88335 features dynamic and automatic on-chip calibration to continually compensate for temperature and process variation s across components. these calibration routines are performed period ically in the course of normal radio operation. examples of s ome of the automatic calibration algorithms are baseband filter calibration for optimum tran smit and receive performance, and loft calibration for carrier leakage reduction. in addition, i/q ca libration, r calibration, and vco calibration are performed on-ch ip. no per-board calibration is required in manufacturi ng test, which helps to minimize the test time and cost in large volume product ion.
document number: 002-15057 rev. *b page 51 of 110 cyw88335 figure 29. radio functional block diagram gm bt ? logen wl ? logen bt ? pll wl ? pll wlan ? bb bt ? bb clb voltage ? regulators bt ? fm lpo/ext ? lpo/rcal wl ? adc bt ? adc bt ? dac wl ? pa wl ? pad wl ? pga wl ? tx ? g \ mixer wl ? dac wl ? a \ pa wl ? a \ pad wl ? a \ pga wl ? tx ? a \ mixer wl ? txlpf wl ? rxlpf wl ? rx ? a \ mixer wl ? rx ? g \ mixer wl ? a \ lna11 wl ? a \ lna12 slna wl ? g \ lna12 bt ? lna ? load bt ? lna ? gm bt ? pa bt ? rx ? mixer bt ? tx ? mixer bt ? rxlpf bt ? txlpf shared ? xo wl ? txlpf wl ? dac wl ? adc wl ? rxlpf wl ? atx wl ? grx wl ? gtx wl ? arx mux bt ? tx bt ? rx bt ? adc bt ? rxlpf bt ? dac
document number: 002-15057 rev. *b page 52 of 110 cyw88335 12. pinout and signal descriptions 12.1 ball maps figure 30 shows the wlbga ball map. figure 30. 145-ball wlbga (top view) 1 23456 7 8 9 10 11 12 a no connect no connect no connect no connect no connect no connect no connect no connect a b sr_pvss sr_vlx wl_reg_on lpo_in gpio_3 gpio_0 hsic_data hsic_strobe rrefhsic sdio_data_0 sdio_clk sdio_cmd b c sr_vddbatp5v sr_vddbata5v pmu_avss gpio_6 gpio_4 gpio_1 wl_vddc hsic_avdd12pll hsic_dvdd12 sdio_data_1 sdio_data_3 wl_vddc c d ldo_vdd1p5 vout_cldo bt_reg_on gpio_7 gpio_5 gpio_2 vssc hsic_agndpll vddio_sd sdio_data_2 vssc rf_sw_ctrl_4 d e vout_3p3 vout_lnldo vssc jtag_sel bt_uart_cts vddio_rf vssc rf_sw_ctrl_8 rf_sw_ctrl_3 rf_sw_ctrl_2 e f vout_btldo2p5 ldo_vddbat5v vddio rf_sw_ctrl_9 bt_uart_rts bt_uart_txd rf_sw_ctrl_5 rf_sw_ctrl_1 rf_sw_ctrl_0 f g bt_pcm_in bt_pcm_clk wl_vddc wl_vddc bt_uart_rxd rf_sw_ctrl_7 wl_vddc bbpll_avs wrf_xtal_gnd1p2 bbpll_avdd1p2 g h gpio_8 bt_pcm_sync clk_req bt_vddio bt_vddc bt_i2s_ws wrf _gpio_out wrf_wl_lnldoin_vdd1p5 rf_sw_ctrl_6 wrf_vco_gnd wrf_xtal_vdd1p5 wrf_xta l_in h j bt_host_wake bt_pcm_out bt_vddc vssc bt_i2s_clk wrf_tssi_a wrf_buck_gnd1p5 wrf_mmd_gnd1p2 wrf_pfd_gnd1p2 wrf_cp_gnd wrf_xtal_out j k bt_dev_wake vssc bt_i2s_di bt_i2s_do wrf_afe_gnd1p2 wrf_lo_gnd1p2_2 wrf_synth_vba t_vdd3p3 wrf_mmd_vdd1p2 wrf_pfd_vdd1p2 wrf_xtal_vdd1p2 k l bt_ifvdd1p2 bt_pllvss bt_ifvss wrf_rx2g_gnd1p2 wrf_tx _gnd1p2 wrf_padrv_vbat_vdd3p3 wrf_padr v_vbat_gnd3p3 wrf_lo_gnd1p2_2 wrf_rx5g_gnd1p 2 l m bt_vcovss bt_pllvdd1p2 bt_pavss bt_agpio wrf_lna_2g_gnd1p2 wrf_pa_vbat_gnd3p3_4 wrf_pa_vbat_gnd3p3_3 wrf_pa_vbat_gnd3p3_2 wrf_pa_vbat_g nd3p3_1 wrf_ lna_5g_gnd1p2 m n bt_vcovdd1p2 bt_lnavdd1p2 bt_rf bt_pavdd2p5 wrf_rfin_2g wrf_rfout_2g wrf_pa2g_vbat_vdd3p3 wrf_pa5g_vbat_vdd3p3 wrf_rfout_5g wrf_rfin_5g n 1 23456 7 8 9 10 11 12 ncf ncf ncf lnf_vdd1p2 lnf_vdd1p2 lnf_vdd1p2 vssf vssf vssf vssf
document number: 002-15057 rev. *b page 53 of 110 cyw88335 12.2 signal descriptions the signal name, type, and description of each pin in the cyw88335 is listed in table 16 . the symbols shown under type indicate pin directions (i/o = bidirectional, i = input, o = output) and th e internal pull-up/pull-down characteristics (pu = weak inter nal pull-up resistor and pd = weak internal pull-down resistor), if any. table 16. wlbga signal descriptions wlbga ball# signal name description type wlan and bluetooth rf signal interface n7 wrf_rfin_2g 2.4 ghz bluetooth and wlan receiver shared input. i n5 bt_rf_tx bluetooth pa output. o n12 wrf_rfin_5g 5 ghz wlan receiver input. i n8 wrf_rfout_2g 2.4 ghz wlan pa output. o n11 wrf_rfout_5g 5 ghz wlan pa output. o j7 wrf_tssi_a 5 ghz tssi input from an optional external power amplifier/power detector. i h7 wrf_res_ext/wrf_gpio_out/ wrf_tssi_g gpio or 2.4 ghz tssi input from an optional external power amplifier/power detector. i/o rf switch control lines f12 rf_sw_ctrl_0 programmable rf switch control lines. the control lines are programmable via the driver and nvram file. o f11 rf_sw_ctrl_1 o e12 rf_sw_ctrl_2 o e11 rf_sw_ctrl_3 o d12 rf_sw_ctrl_4 o f8 rf_sw_ctrl_5 o h9 rf_sw_ctrl_6 o g7 rf_sw_ctrl_7 o e10 rf_sw_ctrl_8 o f5 rf_sw_ctrl_9 o wlan sdio bus interface note: these signals can also have alternate functio nality depending on host interface mode. see table 22 on page 61 for additional details. b11 sdio_clk sdio clock input. i b12 sdio_cmd sdio command line. i/o b10 sdio_data_0 sdio data line 0. i/o c10 sdio_data_1 sdio data line 1. i/o d10 sdio_data_2 sdio data line 2. i/o c11 sdio_data_3 sdio data line 3. i/o
document number: 002-15057 rev. *b page 54 of 110 cyw88335 wlan gpio interface note: the gpio signals can be multiplexed via software and the jtag _sel pin to behave as various specific functions. see table 22 on page 61 for additional details. b6 gpio_0 programmable gpio pins. note: these gpio signals can be configured by software: as either inputs or outputs, to have internal pull-ups or pull-downs enabled or disabled, and to use either a high or low polarity upon assertion. i/o c6 gpio_1 i/o d6 gpio_2 i/o b5 gpio_3 i/o c5 gpio_4 i/o d5 gpio_5 i/o c4 gpio_6 i/o d4 gpio_7 i/o h1 gpio_8 i/o jtag interface e5 jtag_sel jtag select. pull high to select the jtag interface. if the jtag in terface is not used, this pin may be left floating or connected to ground. note: see table 22 on page 61 for additional details. i/o clocks h12 wrf_xtal_in xtal oscillator input. i j12 wrf_xtal_out xtal oscillator output. o b4 lpo_in external sleep clock input (32.768 khz). i h3 clk_req reference clock request (shared by bt and wlan). o bluetooth pcm g2 bt_pcm_clk/bt_pcmclk pcm clock; can be master (output) or slave (input). i/o g1 bt_pcm_in pcm data input. i j3 bt_pcm_out pcm data output. o h2 bt_pcm_sync pcm sync; can be master (output) or slave (input). i/o bluetooth uart e6 bt_uart_cts_n/bt_uart_cts uart clear-to-send. active-low clear-to-send signal for the hci uart interface. i f6 bt_uart_rts_n/ bt_uart_rts/ bt_led uart request-to-send. active-low request-to- send signal for the hci uart interface. bt led control pin. o g6 bt_uart_rxd/ bt_rfdisable2 uart serial input. serial data input for the hci uart interface. bt rf disable pin 2. i f7 bt_uart_txd uart serial output. serial data output for the hci uart interface. o table 16. wlbga signal descriptions (cont.) wlbga ball# signal name description type
document number: 002-15057 rev. *b page 55 of 110 cyw88335 bluetooth/fm i2s j6 bt_i2s_clk i 2 s clock, can be master (output) or slave (input). i/o k6 bt_i2s_do i 2 s data output. i/o k5 bt_i2s_di i 2 s data input. i/o h6 bt_i2s_ws i 2 s ws; can be master (output) or slave (input). i/o bluetooth gpio m6 bt_agpio bt analog gpio pin. i/o miscellaneous b3 wl_reg_on used by pmu to power up or power down the internal cyw88335 regulators used by the wlan section. also, when deasserted, this pin holds the wlan section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. i d3 bt_reg_on used by pmu to power up or power down the internal cyw88335 regulators used by the bluetooth/fm section. also, when deasserted, this pin holds the bluetooth/fm section in reset. this pin has an internal 200 k ? pull-down resistor that is enabled by default. it can be disabled through programming. i k3 bt_dev_wake bluetooth dev_wake. i/o j2 bt_host_wake bluet ooth host_wake. i/o b8 hsic_strobe/strobe unsupported. this pin can be connected to ground or left unconnected (no-connect). i/o b7 hsic_data/data unsupported. this pin can be connected to ground or left unconnected (no-connect). i/o b9 rrefhsic unsupported. leave this pin unconnected (no- connect). i k1 ncf no connect ? l1 ncf no connect ? n2 ncf no connect ? integrated voltage regulators c2 sr_vddbata5v quiet vbat. i c1 sr_vddbatp5v power vbat. i b2 sr_vlx cbuck switching regulator output. refer to table 38 on page 85 for details of the inductor and capacitor required on this output. o d1 ldo_vdd1p5 lnldo input. i f2 ldo_vddbat5v ldo vbat. i h11 wrf_xtal_vdd1p5/wrf_xtal_- buck_vdd1p5 xtal ldo input (1.35v). i k12 wrf_xtal_vdd1p2/wrf_xtal_out_- vdd1p2 xtal ldo output (1.2v). o table 16. wlbga signal descriptions (cont.) wlbga ball# signal name description type
document number: 002-15057 rev. *b page 56 of 110 cyw88335 e2 vout_lnldo output of lnldo. o d2 vout_cldo output of core ldo. o f1 vout_btldo2p5 output of bt ldo. o e1 vout_3p3 ldo 3.3v output. o bluetooth supplies n6 bt_pavdd/bt_pavdd2p5 bluetooth pa power supply. pwr n4 bt_lnavdd/bt_lnavdd1p2 bluetooth lna power supply. pwr l4 bt_ifvdd/bt_ifvdd1p2 bluetooth if block power supply. pwr m4 bt_pllvdd/bt_pllvdd1p2 bluetooth rf pll power supply. pwr n3 bt_vcovdd/bt_vcovdd1p2 bl uetooth rf power supply. pwr supplies n1 lnf_vdd1p2 connect to vout_lnldo output (pin e2). pwr l2 lnf_vdd1p2 connect to vout_lnldo output (pin e2). pwr j1 lnf_vdd1p2 connect to vout_lnldo output (pin e2). pwr wlan supplies h8 wrf_wl_lnldoin_vdd1p5 lnldo 1.35v supply. pwr k9 wrf_synth_vbat_vdd3p3 synth vdd 3.3v supply. pwr l9 wrf_padrv_vbat_vdd3p3 pa driver vbat supply. pwr n10 wrf_pa5g_vbat_vdd3p3 5 ghz pa 3.3v vbat supply. pwr n9 wrf_pa2g_vbat_vdd3p3 2 ghz pa 3.3v vbat supply. pwr k10 wrf_mmd_vdd1p2 1.2v supply. pwr k11 wrf_pfd_vdd1p2 1.2v supply. pwr miscellaneous supplies c7, c12, g4, g5, g8 vddc/wl_vddc 1.2v core supply for wlan. pwr f3 vddio /vddio2 1.8v?3.3v supply for wlan. must be directly connected to pmu_vddio and bt_vddio on the pcb. pwr h5, j4 bt_vddc 1.2v core supply for bt. pwr h4 bt_vddio 1.8v?3.3v supply for bt. must be directly connected to pmu_vddio and vddio on the pcb. pwr d9 vddio_sd 1.8v?3.3v supply for sdio pads. pwr e7 vddio_rf io supply for rf switch control pads (3.3v). pwr c8 avdd12pll/hsic_avdd12pll hsic is not supported. connect this pin to ground to minimize leakage. pwr c9 dvdd12hsic/hsic_dvdd12 hsic is not supported. connect this pin to ground to minimize leakage. pwr g12 bbpll_avdd1p2 1.2v supply for baseband pll. pwr table 16. wlbga signal descriptions (cont.) wlbga ball# signal name description type
document number: 002-15057 rev. *b page 57 of 110 cyw88335 ground h10 wrf_vco_gnd1p2/wrf_vco_gnd vco/logen ground. gnd k7 wrf_afe_gnd1p2 afe ground. gnd j8 wrf_buck_gnd1p5 internal capacitor-less ldo ground. gnd m7 wrf_lna_2g_gnd1p2 2 ghz internal lna ground. gnd m12 wrf_lna_5g_gnd1p2 5 ghz internal lna ground. gnd l8 wrf_tx_gnd1p2 tx ground. gnd l10 wrf_padrv_vbat_gnd3p3 pad ground. gnd g11 wrf_xtal_gnd1p2 xtal ground. gnd l7 wrf_rx2g_gnd1p2 rx 2ghz ground. gnd l12 wrf_rx5g_gnd1p2 rx 5ghz ground. gnd l11 wrf_lo_gnd1p2_1 lo ground. gnd k8 wrf_lo_gnd1p2_2 lo ground. gnd m11 wrf_pa_vbat_gnd3p3_1 pa ground. gnd m10 wrf_pa_vbat_gnd3p3_2 pa ground. gnd m9 wrf_pa_vbat_gnd3p3_3 pa ground. gnd m8 wrf_pa_vbat_gnd3p3_4 pa ground. gnd j9 wrf_mmd_gnd1p2 ground. gnd j11 wrf_cp_gnd1p2/wrf_cp_gnd ground. gnd j10 wrf_pfd_gnd1p2 ground. gnd d7, d11, e3, e8, j5, k4 vssc core ground for wlan and bt. gnd b1 sr_pvss power ground. gnd c3 pmu_avss quiet ground. gnd d8 agnd12pll/hsic_agndpll pll ground. gnd m5 bt_pavss bluetooth pa ground. gnd l6 bt_ifvss bluetooth if block ground. gnd l5 bt_pllvss bluetooth pll ground. gnd m3 bt_vcovss bluetooth vco ground. gnd m1 vssf ground. gnd m2 vssf ground. gnd l3 vssf ground. gnd k2 vssf ground. gnd g10 avss_bbpll/bbpllavss baseband pll ground. gnd no connect a2, a3, a4, a6, a7, a9, a10, a11 nc no connect ? table 16. wlbga signal descriptions (cont.) wlbga ball# signal name description type
document number: 002-15057 rev. *b page 58 of 110 cyw88335 12.3 wlan gpio signals and strapping options the pins listed in ta b l e 1 7 are sampled at power-on reset (por) to determine the various operating modes. sampling occurs a few milliseconds after an internal por or deassertion of the external por. after the por, each pin assumes the gpio or alternative function specified in the signal descriptions table. each str apping option pin has an internal pull-up (pu) or pull-down (pd) r esistor that determines the default mode. to change the mode, connect an external pu resistor to vddio or a pd resistor to gnd, using a 10 k ? resistor or less. note: refer to the reference board schematics for more information. table 17. wlan gpio functions and strapping options pin name wlbga pin # default function description gpio_7 d4 1 sdio_sel a a. see ta b l e 1 8 and table 19 . gpio_8 h1 0 sdio_padvddio sdio_clk b11 1 cpu-less a sdio_data_2 d10 1 spi_sel a table 18. sdio/gspi i/o voltage selection sdio_sel spi_sel sdio_padvddio mode 1x 01.8v i/o 1x 13.3v i/o 01 01.8v i/o 01 13.3v i/o 00 x3.3v i/o table 19. host interface selection (wlbga package) sdio_sel spi_sel cpuless mode 1 x x sdio mode (3.3v or 1.8v i/o) 0 1 x gspi mode (3.3v or 1.8v i/o) 0 0 0 unsupported 0 0 1 unsupported
document number: 002-15057 rev. *b page 59 of 110 cyw88335 12.3.1 multiplexed bluetooth gpio signals the bluetooth gpio pins (bt_gpio_0 to bt _gpio_7) are multiplexed pi ns and can be programmed to be used as gpios or for other bluetooth interface signals such as i 2 s. the specific function for a given bt_gpio_x pin is chosen by programming the pad function control register for that specific pin. ta b l e 2 0 shows the possible options for each bt_gpio_x pin. note that each bt_gpio_x pin's pad function control register setting is independent (bt_gpio_1 can be set to pad function 7 at the same time that bt_gpio_3 is set to pad function 0). when the pad function c ontrol register is set to 0, the bt_gpios do not have specific functions assigned to them and behave as generic gpios. the a_gpio_x pins described below are multiplexed behind the cyw88335's pcm and i 2 s interface pins. table 20. gpio multiplexing matrix pin name pad function control register setting 0 1 2 3 4 5 6 7 15 bt_uart_cts_n uart_cts_n ?????? a_gpio[1] ? bt_uart_rts_n uart_rts_n ?????? a_gpio[0] ? bt_uart_rxd uart_rxd ?????? gpio[5] ? bt_uart_txd uart_txd ?????? gpio[4] ? bt_pcm_in a_gpio[3] pcm_in pcm_in hclk ? ? ? i2s_ssdi/msdi sf_miso bt_pcm_out a_gpio[2] pcm_out pcm_out link_ind ? i2s_msdo ? i2s_ssdo sf_mosi bt_pcm_sync a_gpio[1] pcm_sync pcm_sync hclk int_lpo i2s_mws ? i2s_sws sf_spi_csn bt_pcm_clk a_gpio[0] pcm_clk pcm_clk ?? i2s_msck ? i2s_ssck sf_spi_clk bt_i2s_do a_gpio[5] pcm_out ?? i2s_ssdo i2s_msdo ? status ? bt_i2s_di a_gpio[6] pcm_in ? hclk i2s_ssdi/ msdi ?? tx_con_fx ? bt_i2s_ws gpio[7] pcm_sync ? link_ind ? i2s_mws ? i2s_sws ? bt_i2s_clk gpio[6] pcm_clk ?? int_lpo i2s_msck ? i2s_ssck ? bt_gpio_1 gpio[1] ?????? class1[2] ? bt_gpio_0 gpio[0] ??? clk_12p288 ?? ? ? clk_req wl/ bt_clk_req ?????? a_gpio[7] ?
document number: 002-15057 rev. *b page 60 of 110 cyw88335 the multiplexed gpio signals are described in table 21 . table 21. multiplexed gpio signals pin name type description uart_cts_n i host uart clear to send. uart_rts_n o device uart request to send. uart_rxd i device uart receive data. uart_txd o host uart transmit data. pcm_in i pcm data input. pcm_out o pcm data output. pcm_sync i/o pcm sync signal, can be master (output) or slave (input). pcm_clk i/o pcm clock, can be master (output) or slave (input). gpio[7:0] i/o general-purpose i/o. a_gpio[7:0] i/o a group general-purpose i/o. i2s_msdo o i 2 s master data output. i2s_mws o i 2 s master word select. i2s_msck o i 2 s master clock. i2s_ssck i i 2 s slave clock. i2s_ssdo o i 2 s slave data output. i2s_sws i i 2 s slave word select. i2s_ssdi/msdi i i 2 s slave/master data input. status o signals bluetooth priority status. tx_con_fx i wlan-bt coexist. transmission confirmation; permission for bt to transmit. rf_active o wlan-bt coexist. asserted (logic high) during local bt rx and tx slots. link_ind o bt receiver/transmitter link indicator. clk_req o wlan/bt clock request output. sf_spi_clk o sflash sclk: serial clock (output from master). sf_miso i sflash miso ; somi: master input, slave output (output from slave). sf_mosi o sflash mosi; simo: master out put, slave input (output from master). sf_spi_csn o sflash ss: slave select (active low, output from master).
document number: 002-15057 rev. *b page 61 of 110 cyw88335 12.4 gpio/sdio altern ative signal functions table 22. cyw88335 gpio/sdio al ternative signal functions a b a. n/a = pin not available in this package. b. jtag signals (tck, tdi, tdo, tms, and trst _l) are selected when jtag_sel pin is high. pins wlbga sdio gpio_0 wl_host_wake gpio_1 wl_dev_wake gpio_2 tck, gci_gpio_1, or uart rx gpio_3 tms or gci_gpio_0 gpio_4 tdi or seci_in gpio_5 tdo or seci_out gpio_6 trst_l or uart tx gpio_7 [strap, tied high] gpio_8 [strap, tied high or low] gpio_9 n/a gpio_10 n/a gpio_11 n/a gpio_12 n/a gpio_13 n/a gpio_14 n/a gpio_15 n/a sdio_clk sdio_clk sdio_cmd sdio_cmd sdio_data_0 sdio_data_0 sdio_data_1 sdio_data_1 sdio_data_2 sdio_data_2 sdio_data_3 sdio_data_3
document number: 002-15057 rev. *b page 62 of 110 cyw88335 12.5 i/o states the following notations are used in table 23 : i: input signal o: output signal i/o: input/output signal pu = pulled up pd = pulled down nopull = neither pulled up nor pulled down table 23. i/o states name i/o keeper a active mode low power state/ sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail wl_reg_on i n input; pd (pull-down can be disabled) input; pd (pull-down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? bt_reg_on i n input; pd (pull down can be disabled) input; pd (pull down can be disabled) input; pd (of 200k) input; pd (of 200k) input; pd (of 200k) ? clk_req i/o y open drain or push-pull (programmable). active high. open drain or push-pull (programmable). active high pd open drain. active high open drain. active high. bt_vddio bt_host_wake i/o y input/output; pu, pd, nopull (programmable) input/output; pu, pd, nopull (programmable) high-z, nopull input, pu input, pd bt_vddio bt_dev_wake i/o y input/output; pu, pd, nopull (programmable) input; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd bt_vddio bt_gpio 2, 3, 4, 5 i/o y input/output; pu, pd, nopull (programmable) input/output; pu, pd, nopull (programmable) high-z, nopull input, pd input, pd bt_vddio bt_uart_cts i y input; nopull input; nopull high-z, nopull input; pu input; pu bt_vddio bt_uart_rts o y output; nopull output; nopull high-z, nopull input; pu input; pu bt_vddio bt_uart_rxd i y input; pu input; nopull high-z, nopull input; pu input; pu bt_vddio bt_uart_txd o y output; nopull output; nopull high-z, nopull input; pu input; pu bt_vddio sdio data i/o n input/output; pu (sdio mode) input; pu (sdio mode) high-z, nopull input; pu (sdio mode) input; pu (sdio mode) vddio_sd sdio cmd i/o n input/output; pu (sdio mode) input; pu (sdio mode) high-z, nopull input; pu (sdio mode) input; pu (sdio mode) vddio_sd sdio_clk i n input; nopull input; nopull high-z, nopull input; nopull input; nopull vddio_sd bt_pcm_clk i/o y input; nopull c input; nopull c high-z, nopull output input, pd bt_vddio
document number: 002-15057 rev. *b page 63 of 110 cyw88335 bt_pcm_in i/o y input; nopull c input; nopull c high-z, nopull input; nopull, hi-z input, pd bt_vddio bt_pcm_out i/o y input; nopull c input; nopull c high-z, nopull output input, pd bt_vddio bt_pcm_sync i/o y input; nopull c input; nopull c high-z, nopull output input, pd bt_vddio bt_i2s_ws i/o y pd d pd d high-z, nopull input, pd input, pd bt_vddio bt_i2s_clk i/o y pd d pd d high-z, nopull input, pd input, pd bt_vddio bt_i2s_di i/o y pd d input; pd d high-z, nopull input, pd input, pd bt_vddio bt_i2s_do i/o y output d output d high-z, nopull input, pd input, pd bt_vddio wl gpio_0 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd vddio wl gpio_1 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull vddio wl gpio_2 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull vddio wl gpio_3 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd vddio wl gpio_4 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull vddio wl gpio_5 i/o y input/output; pu, pd, nopull (programmable [default: pd]) input/output; pu, pd, nopull (programmable [default: pd]) high-z, nopull input; pd input; pd vddio wl gpio_6 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull vddio wl gpio_7 i/o y input/output; pu, pd, nopull (programmable [default: nopull]) input/output; pu, pd, nopull (programmable [default: nopull]) high-z, nopull input; nopull input; nopull vddio wl gpio_8 i/o y input/output; pu, pd, nopull (programmable [default: pd]) e input/output; pu, pd, nopull (programmable [default: pd]) e high-z, nopull input; pd e input; pd e vddio table 23. i/o states (cont.) name i/o keeper a active mode low power state/ sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail
document number: 002-15057 rev. *b page 64 of 110 cyw88335 rf_sw_ctrl_x o n output, nopull output, nopull high-z, nopull output, nopull output, nopull vddio_rf a. keeper column: n = pad has no keeper. y = pad has a keeper. keeper is always active except in power-down state. if there is n o keeper, and it is an input and there is nopull, then the pad should be driven to prevent leakage due to floating pad (sdio_clk, for example). b. in the power-down state (xx_reg_on=0): high-z; nopull => the pad is disabled be cause power is not supplied. c. depending on whether the pcm interface is enabled and the configurat ion of pcm is in master or slave mode, it can be either o utput or input. d. depending on whether the i 2 s interface is enabled and the configuration of i 2 s is in master or slave mode, it can be either output or input e. nopull when in sdio mode. table 23. i/o states (cont.) name i/o keeper a active mode low power state/ sleep (all power present) power-down b (bt_reg_on and wl_reg_on held low) out-of-reset; before sw download (bt_reg_on high; wl_reg_on high) (wl_reg_on high and bt_reg_on = 0) and vddios are present power rail
document number: 002-15057 rev. *b page 65 of 110 cyw88335 13. dc characteristics 13.1 absolute maximum ratings caution: the absolute maximum ratings in table 24 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. functional operat ion is not guaranteed under thes e conditions. operation at abso lute maximum conditions for extended periods can advers ely affect long-term reliability of the device. 13.2 environmental ratings the environmental ratings are shown in ta b l e 2 5 . 13.3 electrostatic discharge specifications extreme caution must be exercised to prev ent electrostatic discharge (esd) damage. pr oper use of wrist and heel grounding strap s to discharge static electricity is required when handling these devices. always store unused material in its antistatic packagi ng. table 24. absolute maximum ratings rating symbol value unit dc supply for vbat and pa driver supply a a. the maximum continuous voltage is 4.8v. voltage transients up to 6.0v (for up to 10 seconds), cumulative duration over the li fetime of the device, are allowed. voltage transients as high as 5.0v (for up to 250 seconds), cu mulative duration over the lifetime of the device, are allowed. vbat ?0.5 to +6.0 v dc supply voltage for digital i/o vddio ?0.5 to 3.9 v dc supply voltage for rf switch i/os vddio_rf ?0.5 to 3.9 v dc input supply voltage for cldo and lnldo ? ?0.5 to 1.575 v dc supply voltage for rf analog vdd1p2 ?0.5 to 1.32 v dc supply voltage for core vddc ?0.5 to 1.32 v wrf_tcxo_vdd ? ?0.5 to 3.63 v maximum undershoot voltage for i/o b b. duration not to exceed 25% of the duty cycle. v undershoot ?0.5 v maximum overshoot voltage for i/o b v overshoot vddio + 0.5 v maximum junction temperature t j 125 c table 25. environmental ratings characteristic value units conditions/comments ambient temperature (t a ) ?40 to +85 c functional operation a a. functionality is guaranteed but specifications require derating at extreme temperatures; see t he specification tables for det ails. storage temperature ?40 to +125 c ? relative humidity less than 60 % storage less than 85 % operation table 26. esd specifications pin type symbol condition esd rating unit esd, handling reference: nqy00083, section 3.4, group d9, table b esd_hand_hbm human body model: aec-q100-002 rev-e 1000 v cdm esd_hand_cdm charged device model: aec-q100-011 rev-c1 150 (wlan pins) 250 (non-wlan pins) v mm esd_mm machine model: aec-q100-003 rev-e 30 v
document number: 002-15057 rev. *b page 66 of 110 cyw88335 13.4 recommended operating conditions and dc characteristics caution: functional operation is not guaranteed outside of the limits shown in table 27 and operation outside these limits for extended periods can adversely affect long-term reliability of the device. table 27. recommended operating conditions and dc characteristics parameter symbol value unit minimum typical maximum dc supply voltage for vbat vbat 3.0 a ?4.8 b v dc supply voltage for core vdd 1.14 1.2 1.26 v dc supply voltage for rf blocks in chip vdd1p2 1.14 1.2 1.26 v dc supply voltage for tcxo input buffer wrf_tcxo_vdd 1.62 1.8 1.98 v dc supply voltage for digital i/o vddio, vddio_sd 1.71 ? 3.63 v dc supply voltage for rf switch i/os vddio_rf 3.13 3.3 3.46 v external tssi input wrf_tssi_a, wrf_tssi_g 0.15 ? 0.95 v internal por threshold vth_por 0.4 ? 0.7 v sdio interface i/o pins for vddio_sd = 1.8v: input high voltage vih 1.27 ? ? v input low voltage vil ? ? 0.58 v output high voltage @ 2 ma voh 1.40 ? ? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio_sd = 3.3v: input high voltage vih 0.625 vddio ?? v input low voltage vil ? ? 0.25 vddio v output high voltage @ 2 ma voh 0.75 vddio ?? v output low voltage @ 2 ma vol ? ? 0.125 vddio v other digital i/o pins for vddio = 1.8v: input high voltage vih 0.65 vddio ?? v input low voltage vil ? ? 0.35 vddio v output high voltage @ 2 ma voh vddio ? 0.45 ?? v output low voltage @ 2 ma vol ? ? 0.45 v for vddio = 3.3v: input high voltage vih 2.00 ? ? v input low voltage vil ? ? 0.80 v output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v
document number: 002-15057 rev. *b page 67 of 110 cyw88335 rf switch control output pins c for vddio_rf = 3.3v: output high voltage @ 2 ma voh vddio ? 0.4 ? ? v output low voltage @ 2 ma vol ? ? 0.40 v output capacitance c out ??5 pf a. the cyw88335 is functional across this range of voltages. op timal rf performance specified in the data sheet, however, is gua ranteed only for 3.13v < vbat < 4.8v. b. the maximum continuous voltage is 4.8v. voltage transients up to 6.0v (for up to 10 seconds), cumulative duration over the li fetime of the device are allowed. voltage transients as high as 5.0v (for up to 250 seconds), cu mulative duration over the lifetime of the device are allowed. c. programmable 2 ma to 16 ma drive strength. default is 10 ma. table 27. recommended operating conditions and dc characteristics (cont.) parameter symbol value unit minimum typical maximum
document number: 002-15057 rev. *b page 68 of 110 cyw88335 14. bluetooth rf specifications unless otherwise stated, limit values apply for the conditions specified in table 25 on page 65 and table 27 on page 66 . typical values apply for the following conditions: vbat = 3.6v ambient temperature +25c figure 31. port locations for bluetooth testing note: all bluetooth specifications are measured at the chip port unless otherwise specified. filter rf switch (0.5 db typical insertion loss) antenna port rf port wlan tx bt tx wlan/bt rx chip port cyw88335
document number: 002-15057 rev. *b page 69 of 110 cyw88335 table 28. bluetooth receiver rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unless otherwise specified. general frequency range ? 2402 ? 2480 mhz rx sensitivity gfsk, 0.1% ber, 1 mbps ? ?93.5 ? dbm ? /4?dqpsk, 0.01% ber, 2 mbps ? ?95.5 ? dbm 8?dpsk, 0.01% ber, 3 mbps ? ?89.5 ? dbm input ip3 ? ?16 ? ? dbm maximum input at antenna ? ? ? ?20 dbm rx lo leakage 2.4 ghz band ? ? ?90.0 ?80.0 dbm interference performance a c/i co-channel gfsk, 0.1% ber ? 8 ? db c/i 1-mhz adjacent channel gfsk, 0.1% ber ? ?7 ? db c/i 2-mhz adjacent channel gfsk, 0.1% ber ? ?38 ? db c/i ? 3-mhz adjacent channel gfsk, 0.1% ber ? ?56 ? db c/i image channel gfsk, 0.1% ber ? ?31 ? db c/i 1-mhz adjacent to image channel gfsk, 0.1% ber ? ?46 ? db c/i co-channel ? /4?dqpsk, 0.1% ber ? 9 ? db c/i 1-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?11 ? db c/i 2-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?39 ? db c/i ? 3-mhz adjacent channel ? /4?dqpsk, 0.1% ber ? ?55 ? db c/i image channel ? /4?dqpsk, 0.1% ber ? ?23 ? db c/i 1-mhz adjacent to image channel ? /4?dqpsk, 0.1% ber ? ?43 ? db c/i co-channel 8?dpsk, 0.1% ber ? 17 ? db c/i 1 mhz adjacent cha nnel 8?dpsk, 0.1% ber ? ?4 ? db c/i 2 mhz adjacent channe l 8?dpsk, 0.1% ber ? ?37 ? db c/i ? 3-mhz adjacent channel 8?dpsk, 0.1% ber ? ?53 ? db c/i image channel 8?dpsk, 0.1% ber ? ?16 ? db c/i 1-mhz adjacent to image channel 8?dpsk, 0.1% ber ? ?37 ? db out-of-band blocking performance (cw) 30?2000 mhz 0.1% ber ? ?10.0 ? dbm 2000?2399 mhz 0.1% ber ? ?27 ? dbm 2498?3000 mhz 0.1% ber ? ?27 ? dbm 3000 mhz?12.75 ghz 0.1% ber ? ?10.0 ? dbm
document number: 002-15057 rev. *b page 70 of 110 cyw88335 out-of-band blocking performance, modulated interferer gfsk (1 mbps) b 698?716 mhz wcdma ? ?13.5 ? dbm 776?849 mhz wcdma ? ?13.8 ? dbm 824?849 mhz gsm850 ? ?13.5 ? dbm 824?849 mhz wcdma ? ?14.3 ? dbm 880?915 mhz e-gsm ? ?13.1 ? dbm 880?915 mhz wcdma ? ?13.1 ? dbm 1710?1785 mhz gsm1800 ? ?18.1 ? dbm 1710?1785 mhz wcdma ? ?17.4 ? dbm 1850?1910 mhz gsm1900 ? ?19.4 ? dbm 1850?1910 mhz wcdma ? ?18.8 ? dbm 1880?1920 mhz td-scdma ? ?19.7 ? dbm 1920?1980 mhz wcdma ? ?19.6 ? dbm 2010?2025 mhz td?scdma ? ?20.4 ? dbm 2500?2570 mhz wcdma ? ?20.4 ? dbm 2500?2570 mhz e band 7 ? ?30.5 ? dbm 2300-2400 mhz f band 40 ? ?34.0 ? dbm 2570?2620 mhz c band 38 ? ?30.8 ? dbm 2545?2575 mhz d xgp band ? ?29.5 ? dbm dpsk (2 mbps) b 698?716 mhz wcdma ? ?9.8 ? dbm 776?794 mhz wcdma ? ?9.7 ? dbm 824?849 mhz gsm850 ? ?10.7 ? dbm 824?849 mhz wcdma ? ?11.4 ? dbm 880?915 mhz e-gsm ? ?10.4 ? dbm 880?915 mhz wcdma ? ?10.2 ? dbm 1710?1785 mhz gsm1800 ? ?15.8 ? dbm 1710?1785 mhz wcdma ? ?15.4 ? dbm 1850?1910 mhz gsm1900 ? ?16.6 ? dbm 1850?1910 mhz wcdma ? ?16.4 ? dbm 1880?1920 mhz td-scdma ? ?17.9 ? dbm 1920?1980 mhz wcdma ? ?16.8 ? dbm 2010?2025 mhz td-scdma ? ?18.6 ? dbm 2500?2570 mhz wcdma ? ?20.4 ? dbm 2500?2570 mhz e band 7 ? ?31.9 ? dbm 2300?2400 mhz f band 40 ? ?35.3 ? dbm 2570-2620 mhz c band 38 ? ?31.8 ? dbm 2545-2575 mhz d xgp band ? ?31.1 ? dbm table 28. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit /4
document number: 002-15057 rev. *b page 71 of 110 cyw88335 8dpsk (3 mbps) b 698?716 mhz wcdma ? ?12.6 ? dbm 776?794 mhz wcdma ? ?12.6 ? dbm 824?849 mhz gsm850 ? ?12.7 ? dbm 824?849 mhz wcdma ? ?13.7 ? dbm 880?915 mhz e-gsm ? ?12.8 ? dbm 880?915 mhz wcdma ? ?12.6 ? dbm 1710?1785 mhz gsm1800 ? ?18.1 ? dbm 1710?1785 mhz wcdma ? ?17.4 ? dbm 1850?1910 mhz gsm1900 ? ?19.1 ? dbm 1850?1910 mhz wcdma ? ?18.6 ? dbm 1880?1920 mhz td-scdma ? ?19.3 ? dbm 1920?1980 mhz wcdma ? ?18.9 ? dbm 2010?2025 mhz td-scdma ? ?20.4 ? dbm 2500?2570 mhz wcdma ? ?21.4 ? dbm 2500?2570 mhz e band 7 ? ?31.0 ? dbm 2300?2400 mhz f band 40 ? ?34.5 ? dbm 2570?2620 mhz c band 38 ? ?31.2 ? dbm 2545?2575 mhz d xgp band ? ?30.0 ? dbm spurious emissions 30 mhz?1 ghz ? ?95 ?62 dbm 1?12.75 ghz ? ?70 ?47 dbm 851?894 mhz ? ?147 ? dbm/hz 925?960 mhz ? ?147 ? dbm/hz 1805?1880 mhz ? ?147 ? dbm/hz 1930?1990 mhz ? ?147 ? dbm/hz 2110?2170 mhz ? ?147 ? dbm/hz a. the maximum value represents the actual bluetooth specificat ion required for bluetooth qualification as defined in the versio n 4.1 specification. b. bluetooth reference level is taken at the 3 db rx desense on each of the modulation schemes. c. interferer: 2380 mhz, bw=10 mhz; measured at 2480 mhz. d. interferer: 2355 mhz, bw=10 mhz; measured at 2480 mhz. e. interferer: 2560 mhz, bw=10 mhz; measured at 2480 mhz. f. interferer: 2360 mhz, bw=10 mhz; measured at 2402 mhz. table 28. bluetooth receiver rf specifications (cont.) parameter conditions minimum typical maximum unit
document number: 002-15057 rev. *b page 72 of 110 cyw88335 table 29. bluetooth transmitter rf specifications parameter conditions minimum typical maximum unit note: the specifications in this table are measured at the chip port output unless otherwise specified. general frequency range 2402 ? 2480 mhz basic rate (gfsk) tx power at bluetooth a 11.0 13.0 ? dbm qpsk tx power at bluetooth a 8.0 10.0 ? dbm 8psk tx power at bl uetooth 8.0 10.0 ? dbm power control step 2 4 8 db note: output power is with tca and tssi enabled. gfsk in-band spurious emissions ?20 dbc bw ? ? 0.93 1 mhz edr in-band spurious emissions 1.0 mhz < |m ? n| < 1.5 mhz m ? n = the frequency range for which the spurious emission is measured relative to the transmit center frequency. ? ?38 ?26.0 dbc 1.5 mhz < |m ? n| < 2.5 mhz ? ?31 ?20.0 dbm |m ? n| ? 2.5 mhz b ? ?43 ?40.0 dbm out-of-band spurious emissions 30 mhz to 1 ghz ? ? ? ?36.0 c, d dbm 1 ghz to 12.75 ghz ? ? ? ?30.0 b, e, f dbm 1.8 ghz to 1.9 ghz ? ? ? ?47.0 dbm 5.15 ghz to 5.3 ghz ? ? ? ?47.0 dbm gps band spurious emissions spurious emissions ? ? ?103 ? dbm out-of-band noise floor g 65?108 mhz fm rx ? ?147 ? dbm/hz 776?794 mhz cdma2000 ? ?147 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?147 ? dbm/hz 925?960 mhz e-gsm ? ?147 ? dbm/hz 1570?1580 mhz gps ? ?146 ? dbm/hz 1805?1880 mhz gsm1800 ? ?145 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?144 ? dbm/hz 2110?2170 mhz wcdma ? ?141 ? dbm/hz 2500?2570 mhz band 7 ? ?140 ? dbm/hz 2300?2400 mhz band 40 ? ?140 ? dbm/hz 2570?2620 mhz band 38 ? ?140 ? dbm/hz 2545?2575 mhz xgp band ? ?140 ? dbm/hz a. output power will be 1 db lower at temperatures between ?15c and ?40c. b. the typical number is measured at 3 mhz offset. c. the maximum value represents the value required for bluetooth qualification as defined in the v4.1 specification. d. the spurious emissions during idle mode are the same as specified in table 29 on page 72 . e. specified at the bluetooth antenna port. f. meets this specification usi ng a front-end band-pass filter. g. transmitted power in cellular at the bluetooth antenna port. see figure 31 on page 68 for the location of the port.
document number: 002-15057 rev. *b page 73 of 110 cyw88335 table 30. local oscillator performance parameter minimum typical maximum unit lo performance lock time ? 72 ? ? s initial carrier frequen cy tolerance ? 25 75 khz frequency drift dh1 packet ? 8 25 khz dh3 packet ? 8 40 khz dh5 packet ? 8 40 khz drift rate ? 5 20 khz/50 s frequency deviation 00001111 sequence in payload a a. this pattern represents an average deviation in payload. 140 155 175 khz 10101010 sequence in payload b b. pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 115 140 ? khz channel spacing ? 1 ? mhz table 31. ble rf specifications parameter conditions minimum typical maximum unit frequency range ? 2402 2480 mhz rx sense a a. dirty tx is on. gfsk, 0.1% ber, 1 mbps ? ?95.5 ? dbm tx power b b. ble tx power can be increased to compensate for front-end losses such as bpf, diplexer, switch, etc.). the output is capped a t 12 dbm out. the ble tx power at the antenna port cannot exceed the 10 dbm specification limit. ? ? 8.5 ? dbm mod char: delta f1 average ? 225 255 275 khz mod char: delta f2 max c c. at least 99.9% of all delta f2 max frequency values recorded over 10 packets must be greater than 185 khz ?99.9??% mod char: ratio ? 0.8 0.95 ? %
document number: 002-15057 rev. *b page 74 of 110 cyw88335 15. wlan rf specifications 15.1 introduction the cyw88335 includes an integrated dual-band direct conversion radio that supports the 2.4 ghz and the 5 ghz bands. this sectio n describes the rf characteristics of the 2.4 ghz and 5 ghz radio. unless otherwise stated, lim it values apply for the conditions specified in table 25 on page 65 and table 27 on page 66 . typical values apply for the following conditions: vbat = 3.6v ambient temperature +25c figure 32. port locations showing optional epa and elna (applies to 2.4 ghz and 5 ghz) 15.2 2.4 ghz band general rf specifications table 32. 2.4 ghz band general rf specifications item condition minimum typical maximum unit tx/rx switch time including tx ramp down ? ? 5 s rx/tx switch time including tx ramp up ? ? 2 s power-up and power-down ramp time dsss/cck modulations ? ? < 2 s filter rf switch (0.5 db typical insertion loss) antenna port rf port wlan tx bt tx wlan/bt rx chip port cyw88335
document number: 002-15057 rev. *b page 75 of 110 cyw88335 15.3 wlan 2.4 ghz receiver performance specifications note: the specifications in ta b l e 3 3 are specified at the rf port and include the use of an external fem with lna from the cypress approved-vendor list (avl), unless otherwise specified. results with fems that are not on the cypress avl are not guaranteed. table 33. wlan 2.4 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz rx sensitivity ieee 802.11b (8% per for 1024 octet psdu) a 1 mbps dsss ? ?98.4 ? dbm 2 mbps dsss ? ?96.5 ? dbm 5.5 mbps dsss ? ?93.7 ? dbm 11 mbps dsss ? ?91.4 ? dbm rx sensitivity ieee 802.11g (10% per for 1024 octet psdu) a 6 mbps ofdm ? ?95.5 ? dbm 9 mbps ofdm ? ?94.1 ? dbm 12 mbps ofdm ? ?93.2 ? dbm 18 mbps ofdm ? ?90.6 ? dbm 24 mbps ofdm ? ?87.3 ? dbm 36 mbps ofdm ? ?84.0 ? dbm 48 mbps ofdm ? ?79.3 ? dbm 54 mbps ofdm ? ?77.8 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,b. defined for default parameters: 800 ns gi and non-stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?95.0 ? dbm mcs1 ? ?92.7 ? dbm mcs2 ? ?90.2 ? dbm mcs3 ? ?87.1 ? dbm mcs4 ? ?83.5 ? dbm mcs5 ? ?78.9 ? dbm mcs6 ? ?77.3 ? dbm mcs7 ? ?75.7 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a,c. defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?92.8 ? dbm mcs1 ? ?89.9 ? dbm mcs2 ? ?87.5 ? dbm mcs3 ? ?84.0 ? dbm mcs4 ? ?80.9 ? dbm mcs5 ? ?76.2 ? dbm mcs6 ? ?74.7 ? dbm mcs7 ? ?73.3 ? dbm
document number: 002-15057 rev. *b page 76 of 110 cyw88335 rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,d. defined for default parameters: 800 ns gi and non-stbc 20 mhz channel spacing for all mcs rates mcs0 ? ?94.3 ? dbm mcs1 ? ?91.9 ? dbm mcs2 ? ?90.1 ? dbm mcs3 ? ?86.9 ? dbm mcs4 ? ?83.4 ? dbm mcs5 ? ?78.9 ? dbm mcs6 ? ?77.3 ? dbm mcs7 ? ?75.6 ? dbm mcs8 ? ?71.2 ? dbm rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a,e. defined for default parameters: 800 ns gi and non-stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?91.5 ? dbm mcs1 ? ?89.0 ? dbm mcs2 ? ?87.2 ? dbm mcs3 ? ?84.0 ? dbm mcs4 ? ?80.8 ? dbm mcs5 ? ?76.3 ? dbm mcs6 ? ?74.7 ? dbm mcs7 ? ?73.3 ? dbm mcs8 ? ?68.9 ? dbm mcs9 ? ?67.6 ? dbm rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) at wlan rf port. defined for default param- eters: 800 ns gi, ldpc coding, and non-stbc. mcs7 20 mhz ? ?77.4 ? dbm mcs8 20 mhz ? ?74.7 ? dbm mcs7 40 mhz ? ?74.6 ? dbm mcs8 40 mhz ? ?71.6 ? dbm mcs9 40 mhz ? ?70.1 ? dbm mcs7 80 mhz ? ?71.5 ? dbm mcs8 80 mhz ? ?68.1 ? dbm mcs9 80 mhz ? ?66.0 ? dbm table 33. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 77 of 110 cyw88335 blocking level for 3 db rx sensitivity degradation (without external filtering) f 776?794 mhz cdma2000 ? ?24 ? dbm 824?849 mhz g cdmaone ? ?25 ? dbm 824?849 mhz gsm850 ? ?15 ? dbm 880?915 mhz e-gsm ? ?16 ? dbm 1710?1785 mhz gsm1800 ? ?18 ? dbm 1850?1910 mhz gsm1800 ? ?19 ? dbm 1850?1910 mhz cdmaone ? ?26 ? dbm 1850?1910 mhz wcdma ? ?26 ? dbm 1920?1980 mhz wcdma ? ?28.5 ? dbm 2500?2570 mhz band 7 ? ?45 ? dbm 2300?2400 mhz band 40 ? ?50 ? dbm 2570?2620 mhz band 38 ? ?45 ? dbm 2545?2575 mhz xgp band ? ?45 ? dbm in-band static cw jammer immunity (fc ? 8 mhz < fcw < + 8 mhz) rx per < 1%, 54 mbps ofdm, 1000 octet psdu for: (rxsens + 23 db < rxlevel < max input level) ?80 ? ? dbm input in-band ip3 a maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 2.4 ghz @ 1, 2 mbps (8% per, 1024 octets) ?3.5 ? ? dbm @ 5.5, 11 mbps (8% per, 1024 octets) ?9.5 ? ? dbm @ 6?54 mbps (10% per, 1024 octets) ?9.5 ? ? dbm @ mcs0?7 rates (10% per, 4095 octets) ?9.5 ? ? dbm @ mcs8?9 rates (10% per, 4095 octets) ?11.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection? dsss (difference between interfering and desired signal at 8% per for 1024 octet psdu with desired signal level as specified in condition/notes) desired and interfering signal 30 mhz apart 1 mbps dsss ?74 dbm 35 ? ? db 2 mbps dsss ?74 dbm 35 ? ? db desired and interfering signal 25 mhz apart 5.5 mbps dsss ?70 dbm 35 ? ? db 11 mbps dsss ?70 dbm 35 ? ? db adjacent channel rejection? ofdm (difference between interfering and desired signal (25 mhz apart) at 10% per for 1024 octet psdu with desired signal level as specified in condition/ notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db table 33. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 78 of 110 cyw88335 adjacent channel rejection mcs0?9 (difference between interfering and desired signal (25 mhz apart) at 10% per for 4096 octet psdu with desired signal level as specified in condition/notes) mcs0 ?79 dbm 16 ? ? db mcs1 ?76 dbm 13 ? ? db mcs2 ?74 dbm 11 ? ? db mcs3 ?71 dbm 8 ? ? db mcs4 ?67 dbm 4 ? ? db mcs5 ?63 dbm 0 ? ? db mcs6 ?62 dbm ?1 ? ? db mcs7 ?61 dbm ?2 ? ? db mcs8 ?59 dbm ?4 ? ? db mcs9 ?57 dbm ?6 ? ? db maximum receiver gain ? ? ? 95 ? db gain control step ? ? ? 3 ? db rssi accuracy h range ?95 dbm i to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db return loss z o = 50 ? , across the dynamic range 10 11.5 13 db receiver cascaded noise figure at maximum gain ? 4 ? db a. derate by 1.5 db for ?40c to ?10c and 55c to 85c. b. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. c. sensitivity degradations for al ternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. d. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. e. sensitivity degradations for alternate settings in mcs modes. mm: 0.5 db drop, and sgi: 2 db drop. f. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any specific usag e of each band in any specific country. g. the blocking levels are valid for channels 1 to 11. (for hig her channels, the performance may be lower due to third harmonic signals (3 824 mhz) falling within band.) h. the minimum and maximum values shown have a 95% confidence level. i. ?95 dbm with calibration at the time of manufacture, ?92 dbm without calibration. table 33. wlan 2.4 ghz receiver pe rformance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 79 of 110 cyw88335 15.4 wlan 2.4 ghz transmitter performance specifications note: the specifications in ta b l e 3 4 include the use of the cyw88335's internal pas and are specified at the chip port. table 34. wlan 2.4 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 2400 ? 2500 mhz transmitted power in cellular and fm bands (at 18.5 dbm, 100% duty cycle, 1 mbps cck) a 76?108 mhz fm rx ? ?148.5 ? dbm/hz 776?794 mhz ? ? ?126.5 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?162.5 ? dbm/hz 925?960 mhz e-gsm ? ?162.5 ? dbm/hz 1570?1580 mhz gps ? ?149.5 ? dbm/hz 1805?1880 mhz gsm1800 ? ?140.5 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?137.5 ? dbm/hz 2110?2170 mhz wcdma ? ?128.5 ? dbm/hz 2500?2570 mhz band 7 ? ?104.5 ? dbm/hz 2300?2400 mhz band 40 ? ?94.5 ? dbm/hz 2570?2620 mhz band 38 ? ?119.5 ? dbm/hz 2545?2575 mhz xgp band ? ?109.5 ? dbm/hz harmonic level (at 18 dbm with 100% duty cycle) 4.8?5.0 ghz 2nd harmonic ? ?7.5 ? dbm/1 mhz 7.2?7.5 ghz 3rd harmonic ? ?17.5 ? dbm/1 mhz evm does not exceed tx power at the chip port for highest power level setting at 25c and vbat = 3.6v with spectral mask and evm compliance b, c 802.11b (dsss/cck) ?9 db ? 21.5 ? dbm ofdm, bpsk ?8 db ? 20 ? dbm ofdm, qpsk ?13 db ? 20 ? dbm ofdm, 16-qam ?19 db ? 19 ? dbm ofdm, 64-qam (r = 3/4) ?25 db ? 19 ? dbm ofdm, 64-qam (mcs7, ht20) ?27 db ? 19 ? dbm ofdm, 256-qam (mcs8, vht20) ?30 db ? 17 ? dbm ofdm, 256-qam (mcs8, vht40) ?32 db ? 17 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ? 0.45 ? degrees rms tx power control dynamic range ?10??db closed-loop tx power variation at highest power level setting across full temperature and voltage range. applies across 10 dbm to 20 dbm output power range. ? ? 1.5 db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db
document number: 002-15057 rev. *b page 80 of 110 cyw88335 15.5 wlan 5 ghz receiver pe rformance specifications 4 note: the specifications in ta b l e 3 5 are specified at the rf port and include the use of an external fem with lna from the cypress approved-vendor list (avl), unless otherwise specified. results with fems that are not on the cypress avl are not guaranteed. return loss at chip port tx z o = 50 ? ?6? db a. the cellular standards listed indicate only typical usages of that band in some count ries. other standards may also be used w ithin those bands. b. derate by 1.5 db for temperatures less than ?10c or more th an 55c, or voltages less than 3.0v. derate by 3.0 db for voltages of less than 2.7v, or voltages of less than 3.0v at temperatures less than ?10c or greater than 55c. derate by 4.5 db for ?40c to ?30c. c. tx power for channel 1 and channel 11 is specified by nonvolatile memory parameters. table 35. wlan 5 ghz receiver performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz rx sensitivity ieee 802.11a (10% per for 1000 octet psdu) a 6 mbps ofdm ? ?94.5 ? dbm 9 mbps ofdm ? ?93.1 ? dbm 12 mbps ofdm ? ?92.2 ? dbm 18 mbps ofdm ? ?89.6 ? dbm 24 mbps ofdm ? ?86.3 ? dbm 36 mbps ofdm ? ?83 ? dbm 48 mbps ofdm ? ?78.3 ? dbm 54 mbps ofdm ? ?76.8 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default param- eters: 800 ns gi and non- stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?94 ? dbm mcs1 ? ?91.7 ? dbm mcs2 ? ?89.2 ? dbm mcs3 ? ?86.1 ? dbm mcs4 ? ?82.5 ? dbm mcs5 ? ?77.9 ? dbm mcs6 ? ?76.3 ? dbm mcs7 ? ?74.7 ? dbm rx sensitivity ieee 802.11n (10% per for 4096 octet psdu) a defined for default param- eters: 800 ns gi and non- stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?91.8 ? dbm mcs1 ? ?88.9 ? dbm mcs2 ? ?86.5 ? dbm mcs3 ? ?83.0 ? dbm mcs4 ? ?79.9 ? dbm mcs5 ? ?75.2 ? dbm mcs6 ? ?73.7 ? dbm mcs7 ? ?72.3 ? dbm table 34. wlan 2.4 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 81 of 110 cyw88335 rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default param- eters: 800 ns gi and non- stbc. 20 mhz channel spacing for all mcs rates mcs0 ? ?93.3 ? dbm mcs1 ? ?90.3 ? dbm mcs2 ? ?87.9 ? dbm mcs3 ? ?84.9 ? dbm mcs4 ? ?81.4 ? dbm mcs5 ? ?76.7 ? dbm mcs6 ? ?75.1 ? dbm mcs7 ? ?74.6 ? dbm mcs8 ? ?70.2 ? dbm rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default param- eters: 800 ns gi and non- stbc. 40 mhz channel spacing for all mcs rates mcs0 ? ?90.5 ? dbm mcs1 ? ?87.4 ? dbm mcs2 ? ?85.3 ? dbm mcs3 ? ?82.1 ? dbm mcs4 ? ?79 ? dbm mcs5 ? ?73.9 ? dbm mcs6 ? ?72.4 ? dbm mcs7 ? ?72.3 ? dbm mcs8 ? ?67.9 ? dbm mcs9 ? ?66.6 ? dbm rx sensitivity ieee 802.11ac (10% per for 4096 octet psdu) a defined for default param- eters: 800 ns gi and non- stbc. 80 mhz channel spacing for all mcs rates mcs0 ? ?87 ? dbm mcs1 ? ?83.9 ? dbm mcs2 ? ?81.9 ? dbm mcs3 ? ?78.1 ? dbm mcs4 ? ?75 ? dbm mcs5 ? ?73 ? dbm mcs6 ? ?68.5 ? dbm mcs7 ? ?68.5 ? dbm mcs8 ? ?64.3 ? dbm mcs9 ? ?62.7 ? dbm rx sensitivity ieee 802.11ac 20/40/80 mhz channel spacing with ldpc (10% per for 4096 octet psdu) at wlan rf port. defined for default parameters: 800 ns gi, ldpc coding and non- stbc. mcs7 20 mhz ? ?76.4 ? dbm mcs8 20 mhz ? ?73.7 ? dbm mcs7 40 mhz ? ?73.6 ? dbm mcs8 40 mhz ? ?70.6 ? dbm mcs9 40 mhz ? ?69.1 ? dbm mcs7 80 mhz ? ?70.5 ? dbm mcs8 80 mhz ? ?67.1 ? dbm mcs9 80 mhz ? ?65.0 ? dbm table 35. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 82 of 110 cyw88335 blocking level for 1 db rx sensitivity degradation (without external filtering) b 776?794 mhz cdma2000 ?21 ? ? dbm 824?849 mhz cdmaone ?20 ? ? dbm 824?849 mhz gsm850 ?12 ? ? dbm 880?915 mhz e-gsm ?12 ? ? dbm 1710?1785 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz gsm1800 ?15 ? ? dbm 1850?1910 mhz cdmaone ?20 ? ? dbm 1850?1910 mhz wcdma ?21 ? ? dbm 1920?1980 mhz wcdma ?21 ? ? dbm 2500?2570 mhz band 7 ?21 ? ? dbm 2300?2400 mhz band 40 ?21 ? ? dbm 2570?2620 mhz band 38 ?21 ? ? dbm 2545?2575 mhz xgp band ?21 ? ? dbm input in-band ip3 a maximum lna gain ? ?15.5 ? dbm minimum lna gain ? ?1.5 ? dbm maximum receive level @ 5.24 ghz @ 6, 9, 12 mbps ?9.5 ? ? dbm @ 18, 24, 36, 48, 54 mbps ?14.5 ? ? dbm lpf 3 db bandwidth ? 9 ? 36 mhz adjacent channel rejection (difference between inter- fering and desired signal (20 mhz apart) at 10% per for 1000 octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?79 dbm 16 ? ? db 9 mbps ofdm ?78 dbm 15 ? ? db 12 mbps ofdm ?76 dbm 13 ? ? db 18 mbps ofdm ?74 dbm 11 ? ? db 24 mbps ofdm ?71 dbm 8 ? ? db 36 mbps ofdm ?67 dbm 4 ? ? db 48 mbps ofdm ?63 dbm 0 ? ? db 54 mbps ofdm ?62 dbm ?1 ? ? db 65 mbps ofdm ?61 dbm ?2 ? ? db alternate adjacent channel rejection (difference between inter- fering and desired signal (40 mhz apart) at 10% per for 1000 c octet psdu with desired signal level as specified in condition/notes) 6 mbps ofdm ?78.5 dbm 32 ? ? db 9 mbps ofdm ?77.5 dbm 31 ? ? db 12 mbps ofdm ?75.5 dbm 29 ? ? db 18 mbps ofdm ?73.5 dbm 27 ? ? db 24 mbps ofdm ?70.5 dbm 24 ? ? db 36 mbps ofdm ?66.5 dbm 20 ? ? db 48 mbps ofdm ?62.5 dbm 16 ? ? db 54 mbps ofdm ?61.5 dbm 15 ? ? db 65 mbps ofdm ?60.5 dbm 14 ? ? db maximum receiver gain ? ? 95 ? db gain control step ? ? 3 ? db rssi accuracy d range ?95 dbm e to ?30 dbm ?5 ? 5 db range above ?30 dbm ?8 ? 8 db table 35. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 83 of 110 cyw88335 15.6 wlan 5 ghz transmitter performance specifications note: the specifications in ta b l e 3 5 include the use of the cyw88335's internal pas and are specified at the chip port. return loss z o = 50 ? , across the dynamic range 10 ? 13 db receiver cascaded noise figure at maximum gain ? 4 6 db a. derate by 1.5 db for ?40c to ?10c and 55c to 85c. b. the cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that b and for the purpose of this test. it is not intended to indicate any specific usag e of each band in any specific country. c. for 65 mbps, the size is 4096. d. the minimum and maximum values shown have a 95% confidence level. e. ?95 dbm with calibration at the time of manufacture, ?92 dbm without calibration. table 36. wlan 5 ghz transmitter performance specifications parameter condition/notes minimum typical maximum unit frequency range ? 4900 ? 5845 mhz transmitted power in cellular and fm bands (at 18.5 dbm) a 76?108 mhz fm rx ? ?161.5 ? dbm/hz 776?794 mhz ? ? ?161.5 ? dbm/hz 869?960 mhz cdmaone, gsm850 ? ?161.5 ? dbm/hz 925?960 mhz e-gsm ? ?161.5 ? dbm/hz 1570?1580 mhz gps ? ?161.5 ? dbm/hz 1805?1880 mhz gsm1800 ? ?159.5 ? dbm/hz 1930?1990 mhz gsm1900, cdmaone, wcdma ? ?161.5 ? dbm/hz 2110?2170 mhz wcdma ? ?158.5 ? dbm/hz 2400?2483 mhz bt/wlan ? ?156.5 ? dbm/hz 2500?2570 mhz band 7 ? ?156.5 ? dbm/hz 2300?2400 mhz band 40 ? ?156.5 ? dbm/hz 2570?2620 mhz band 38 ? ?156.5 ? dbm/hz 2545?2575 mhz xgp band ? ?156.5 ? dbm/hz harmonic level (at 17 dbm) 9.8?11.570 ghz 2nd harmonic ? ?30.5 ? dbm/mhz tx power at the chip port for highest power level setting at 25c and vbat = 3.6v with spectral mask and evm compliance b, c ofdm, qpsk ?13 db ? 21.5 ? dbm ofdm, 16-qam ?19 db ? 19 ? dbm ofdm, 64-qam (r = 3/4) ?25 db ? 19 ? dbm ofdm, 64-qam (mcs7, ht20) ?27 db ? 19 ? dbm ofdm, 256-qam (mcs8, vht80) ?30 db ? 17 ? dbm ofdm, 256-qam (mcs9, vht40 and vht80) ?32 db ? 17 ? dbm phase noise 37.4 mhz crystal, integrated from 10 khz to 10 mhz ?0.45? degrees rms table 35. wlan 5 ghz receiver performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 84 of 110 cyw88335 15.7 general spurious emissions specifications tx power control dynamic range ?10??db closed loop tx power variation at highest power level setting across full-temperature and voltage range. applies across 10 to 20 dbm output power range. ??2.0db carrier suppression ? 15 ? ? dbc gain control step ? ? 0.25 ? db return loss z o = 50 ? ?6? db a. the cellular standards listed indicate only typical usages of that band in some count ries. other standards may also be used w ithin those bands. b. derate by 1.5 db for temperatures less than ?10c or more than 55c, or voltages less than 3.0v. derate by 3.0 db for voltage s of less than 2.7v, or voltages of less than 3.0v at temperatures less than ?10c or greater than 55c. derate by 4.5 db for ?40c to ?30c. c. tx power for channel 1 and channel 11 is s pecified by non-volatile memory parameters. table 37. general spurious emissions specifications parameter condition/notes min. typ. max. unit frequency range ? 2400 ? 2500 mhz general spurious emissions tx emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?93 ? dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?45.5 ? dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?72 ? dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?87 ? dbm rx/standby emissions 30 mhz < f < 1 ghz rbw = 100 khz ? ?107 ? dbm 1 ghz < f < 12.75 ghz rbw = 1 mhz ? ?65 a a. the value presented in this table is the result of lo leakage at 3/2 * f c for 2.4 ghz or 2/3 * f c for 5 ghz (where f c is the carrier frequency). for all other emissions in this range, the value is ?96 dbm. ?dbm 1.8 ghz < f < 1.9 ghz rbw = 1 mhz ? ?87 ? dbm 5.15 ghz < f < 5.3 ghz rbw = 1 mhz ? ?100 ? dbm table 36. wlan 5 ghz transmitter performance specifications (cont.) parameter condition/notes minimum typical maximum unit
document number: 002-15057 rev. *b page 85 of 110 cyw88335 16. internal regulator electrical specifications functional operation is not guarant eed outside of the specification limits provided in this section. 16.1 core buck switching regulator table 38. core buck switching regulator (cbuck) specifications specification notes min. typ. max. units input supply voltage (dc) dc voltage range inclusive of disturbances. 3.0 3.6 4.8 a a. the maximum continuous voltage is4.8v. voltage transients up to 6.0v (for up to 10 seconds), cumulative duration over the lif etime of the device, are allowed. voltage transients as high as 5.0v (for up to 250 seconds), cumu lative duration over the lifetime of the device, are allowed. v pwm mode switching frequency ccm, load > 100 ma vbat = 3.6v 2.8 4 5.2 mhz pwm output current ? ? ? 600 ma output current limit ? ? 1400 ma output voltage range programmable, 30 mv steps default = 1.35v 1.2 1.35 1.5 v pwm output voltage dc accuracy includes load and line regulation. forced pwm mode ?4 ? 4 % pwm ripple voltage, static measure with 20 mhz bandwidth limit. static load. max. ripple based on vbat = 3.6v, vout = 1.35v, fsw = 4 mhz, 2.2 h inductor l > 1.05 h, cap + board total-esr < 20 m ? , c out > 1.9 f, esl<200ph ?720mvpp pwm mode peak efficiency peak efficiency at 200 ma load 78 86 ? % pfm mode efficiency 10 ma load current 70 81 ? % start-up time from power down vio already on and steady. time from reg_on rising edge to cldo reaching 1.2v ??850s external inductor 0806 size, 30%, 0.11 25% ohms ? 2.2 ? h external output capacitor ceramic, x5r, 0402, esr <30 m ? at 4 mhz, 20%, 6.3v 2.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 c c. total capacitance includes those connect ed at the far end of the active load. f external input capacitor for sr_vddbatp5v pin, ceramic, x5r, 0603, esr < 30 m ? at 4 mhz, 20%, 6.3v, 4.7 f 0.67 b 4.7 ? f input supply voltage ramp-up time 0 to 4.3v 40 ? ? s
document number: 002-15057 rev. *b page 86 of 110 cyw88335 16.2 3.3v ldo (ldo3p3) table 39. ldo3p3 specifications specification notes min. typ. max. units input supply voltage, v in min. = v o + 0.2v = 3.5v dropout voltage requirement must be met under maximum load for performance specifications. 3.0 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltage transients up to 6.0v (for up to 10 seconds), cumulative duration over the li fetime of the device, are allowed. voltage transients as high as 5.0v (for up to 250 seconds), cumu lative duration over the lifetime of the device, are allowed. v output current ? 0.001 ? 450 ma nominal output voltage, v o default = 3.3v ? 3.3 ? v dropout voltage at max load. ? ? 200 mv output voltage dc accuracy includes line/load regulation. ?5 ? +5 % quiescent current no load ? ? 100 a line regulation v in from (v o + 0.2v) to 4.8v, max load ? ? 3.5 mv/v load regulation load from 1 ma to 450 ma ? ? 0.3 mv/ma psrr v in v o + 0.2v, v o = 3.3v, c o = 4.7 f, max. load, 100 hz to 100 khz 20 ? ? db ldo turn-on time chip already powered up. ? 160 250 s external output capacitor, c o ceramic, x5r, 0402, (esr: 5 m ? ?240 m ? ), 10%, 10v 1.0 b b. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 10 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30m-200 m ? ), 10%, 10v. not needed if sharing vbat capacitor 4.7 f with sr_vddbatp5v. ?4.7? f
document number: 002-15057 rev. *b page 87 of 110 cyw88335 16.3 2.5v ldo (btldo2p5) table 40. btldo2p5 specifications specification notes min. typ. max. units input supply voltage min. = 2.5v + 0.2v = 2.7v. dropout voltage requirement must be met under maximum load for performance speci- fications. 3.0 3.6 4.8 a a. the maximum continuous voltage is 4.8v. voltage transients up to 6.0v (for up to 10 seconds), cumulative duration over the li fetime of the device, are allowed. voltage transients as high as 5.0v (for up to 250 seconds), cu mulative duration over the lifetime of the device, are allowed. v nominal output voltage default = 2.5v. ? 2.5 ? v output voltage programmability range 2.2 2.5 2.8 v accuracy at any step (including line/load regulation), load > 0.1 ma. ?5 ? 5 % dropout voltage at maximum load. ? ? 200 mv output current ? 0.1 ? 70 ma quiescent current no load. ? 8 16 a maximum load at 70 ma. ? 660 700 a leakage current power-down mode. ? 1.5 5 a line regulation v in from (v o + 0.2v) to 4.8v, maximum load. ??3.5mv/v load regulation load from 1 ma to 70 ma, v in = 3.6v. ??0.3mv/ma psrr v in v o + 0.2v, v o = 2.5v, c o = 2.2 f, maximum load, 100 hz to 100 khz. 20 ? ? db ldo turn-on time chip already powered up. ? ? 150 s in-rush current v in = v o + 0.15v to 4.8v, c o = 2.2 f, no load. ? ? 250 ma external output capacitor, c o ceramic, x5r, 0402, (esr: 5?240 m ? ), 10%, 10v 0.7 b b. the minimum value refers to the residual capacitor value afte r taking into account part-to-part tolerance, dc-bias, temperatu re, and aging. 2.2 2.64 f external input capacitor for sr_vddbata5v pin (shared with bandgap) ceramic, x5r, 0402, (esr: 30?200 m ? ), 10%, 10v. not needed if sharing vbat 4.7 f capacitor with sr_vddbatp5v. ?4.7? f
document number: 002-15057 rev. *b page 88 of 110 cyw88335 16.4 cldo table 41. cldo specifications specification notes min. typ. max. units input supply voltage, v in min. = 1.2 + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.31.351.5 v output current ? 0.2 ? 300 ma output voltage, v o programmable in 25 mv steps. default = 1.2.v 1.1 1.2 1.275 v dropout voltage at max. load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ?24?a 300 ma load ? 2.1 ? ma line regulation v in from (v o + 0.15v) to 1.5v, maximum load ? ? 5 mv/v load regulation load from 1 ma to 300 ma ? 0.02 0.05 mv/ma leakage current power down ? ? 20 a bypass mode ? 1 3 a psrr @1 khz, vin 1.35v, c o = 4.7 f 20 ? db start-up time of pmu vio up and steady. time from the reg_on rising edge to the cldo reaching 1.2v. ??700s ldo turn-on time ldo turn-on time when rest of the chip is up ? 140 180 s external output capacitor, c o total esr: 5 m ? ?240 m ? 1.32 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 4.7 ? f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. ?12.2f
document number: 002-15057 rev. *b page 89 of 110 cyw88335 16.5 lnldo table 42. lnldo specifications specification notes min. typ. max. units input supply voltage, vin min. = 1.2v o + 0.15v = 1.35v dropout voltage requirement must be met under maximum load. 1.3 1.35 1.5 v output current ? 0.1 ? 150 ma output voltage, v o programmable in 25 mv steps. default = 1.2v 1.1 1.2 1.275 v dropout voltage at maximum load ? ? 150 mv output voltage dc accuracy includes line/load regulation ?4 ? +4 % quiescent current no load ?44? a max. load ? 970 990 a line regulation v in from (v o + 0.1v) to 1.5v, max load ? ? 5 mv/v load regulation load from 1 ma to 150 ma ? 0.02 0.05 mv/ma leakage current power-down ? ? 10 a output noise @30 khz, 60?150 ma load c o = 2.2 f @100 khz, 60?150 ma load c o = 2.2 f ? ? 60 35 nv/rt hz nv/rt hz psrr @ 1khz, input > 1.35v, c o = 2.2 f, v o = 1.2v 20 ? ? db ldo turn-on time ldo turn-on time when rest of chip is up ? 140 180 s external output capacitor, c o total esr (trace/capacitor): 5 m ? ?240 m ? 0.5 a a. minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, dc-bias, temperature, and aging. 2.2 4.7 f external input capacitor only use an external input capacitor at the vdd_ldo pin if it is not supplied from cbuck output. total esr (trace/capacitor): 30 m ? ?200 m ? ? 1 2.2 f
document number: 002-15057 rev. *b page 90 of 110 cyw88335 17. system power consumption note: unless otherwise stated, these values apply for the conditions specified in table 27 on page 66 . 17.1 wlan current consumption ta b l e 4 3 shows the typical, total current consumed by the cyw88335. to calculate total-solution current consumption for designs using external pas, lnas, and/or fems, add the current c onsumption of the external devices to the numbers in table 43 . all values in ta b l e 4 3 are with the bluetooth core in reset (that is, with bluetooth off). table 43. typical wlan current consumption (cyw88335 current only) mode bandwidth (mhz) band (ghz) vbat = 3.6v, vddio = 1.8v, t a 25c vbat, ma vio a , a a. vio is specified with all pins idle ( not switching) and not driving any loads. sleep modes off b b. wl_reg_on, bt_reg_on low. ? ? 0.005 5 sleep c c. idle, not associated, or inter-beacon. ? ? 0.005 150 ieee power save, dtim 1 d d. beacon interval = 102.4 ms. beacon duration = 1 ms @1 m bps. average current over the specified dtim intervals. ? 2.4 0.850 150 ieee power save, dtim 3 d ?2.4 0. 350 150 ieee power save, dtim 1 d ? 5 0.550 150 ieee power save, dtim 3 d ? 5 0.300 150 active modes receive e,f mcs8 (sgi) e. measured using packet engine test mode. f. duty cycle is 100%. carrier sense (cs) detect/packet receive. 20 2.4 50 5 crs g g. carrier sense (cca) when no carrier present. 20 2.4 46 5 receive e,f mcs7 (sgi) 20 5 66 5 crs g 20 5 56 5 receive e,f mcs7 (sgi) 40 5 79.5 5 crs g 40 5 67 5 receive e,f mcs9 (sgi) 80 5 110 5 crs g 80 5 103 5 active modes with external pas (tx output power is ?5 dbm at the chip port) transmit, cck 20 2.4 88 5 transmit, mcs8, ht20, sgi e, h h. duty cycle is 100%. excludes external pa contribution. 20 2.4 76 5 transmit, mcs7, sgi e, h 20 5 111 5 transmit, mcs7 e, h 40 5 125 5 transmit, mcs9, sgi e, h 40 5 125 5 transmit, mcs9, sgi e, h 80 5 147 5 active modes with internal pas (tx output power measured at the chip port) tx cck 11 mbps at 21.7 dbm 20 2.4 325 5 tx ofdm mcs8 (sgi) at 17.2 dbm 20 2.4 240 5 tx ofdm mcs7 (sgi) at 18.5 dbm 20 5 280 5 tx ofdm mcs7 at 18.7 dbm 40 5 340 5 tx ofdm mcs9 (sgi) at 16.2 dbm 40 5 270 5 tx ofdm mcs9 (sgi) at 15.7 dbm 80 5 270 5
document number: 002-15057 rev. *b page 91 of 110 cyw88335 17.2 bluetooth current consumption the bluetooth ble current consumption measurements are shown in ta b l e 4 4 . note: the wlan core is in reset (wlan_reg_on = low) for all measurements provided in table 44 . the bt current consumption numbers are me asured based on gfsk tx output power = 10 dbm. table 44. bluetooth ble current consumption operating mode vbat (vbat = 3.6v) typical vddio (vddio = 1.8v) typical units sleep 10 225 a standard 1.28s inquiry scan 180 235 a p and i scan b 320 235 a 500 ms sniff master 170 250 a 500 ms sniff slave 120 250 a dm1/dh1 master 22.81 0.034 ma dm3/dh3 master 28.06 0.044 ma dm5/dh5 master 29.01 0.047 ma 3dh5 master 27.09 0.100 ma sco hv3 master 7.9 0.123 ma hv3 + sniff + scan a a. at maximum class 1 tx power, 500 ms sniff, four attempts (slave), p = 1.28s, and i = 2.56s. 11.38 0.180 ma ble scan b b. no devices present. a 1.28 second inte rval with a scan window of 11.25 ms. 175 235 a ble scan 10 ms 14.09 0.022 ma ble adv?unconnectable 1.00 sec 69 245 a ble adv?unconnectable 1.28 sec 67 235 a ble adv?unconnectable 2.00 sec 42 240 a ble connected 7.5 ms 4.30 0.020 ma ble connected 1 sec 53 240 a ble connected 1.28 sec 48 240 a
document number: 002-15057 rev. *b page 92 of 110 cyw88335 18. interface timing an d ac characteristics 18.1 sdio/gspi timing 18.1.1 sdio default mode timing sdio default mode timing is shown by the combination of figure 33 and table 45 . figure 33. sdio bus timing (default mode) table 45. sdio bus timing a parameters (default mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referred to minimum vih and maximum vil b ) b. min. (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 25 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 10 ? ? ns clock high time twh 10 ? ? ns clock rise time ttlh ? ? 10 ns clock fall time tthl ? ? 10 ns inputs: cmd, dat (referenced to clk) input setup time tisu 5 ? ? ns input hold time tih 5 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly 0 ? 14 ns output delay time ? identification mode todly 0 ? 50 ns t wl t wh f pp t thl t isu t tlh t ih t odly (max) t odly (min) input output sdio_clk
document number: 002-15057 rev. *b page 93 of 110 cyw88335 18.1.2 sdio high-speed mode timing sdio high-speed mode timing is shown by the combination of figure 34 and table 46 on page 93 . figure 34. sdio bus timing (high-speed mode) table 46. sdio bus timing a parameters (high-speed mode) a. timing is based on cl ? 40pf load on cmd and data. parameter symbol minimum typical maximum unit sdio clk (all values are referre d to minimum vih and maximum vil b ) b. min. (vih) = 0.7 vddio and max (vil) = 0.2 vddio. frequency ? data transfer mode fpp 0 ? 50 mhz frequency ? identification mode fod 0 ? 400 khz clock low time twl 7 ? ? ns clock high time twh 7 ? ? ns clock rise time ttlh ? ? 3 ns clock fall time tthl ? ? 3 ns inputs: cmd, dat (referenced to clk) input setup time tisu 6 ? ? ns input hold time tih 2 ? ? ns outputs: cmd, dat (referenced to clk) output delay time ? data transfer mode todly ? ? 14 ns output hold time toh 2.5 ? ? ns total system capacitance (each line) cl ? ? 40 pf t wl t wh f pp t thl t isu t tlh t ih t odly input output 50% ? vdd t oh sdio_clk
document number: 002-15057 rev. *b page 94 of 110 cyw88335 18.1.3 sdio bus timing specifications in sdr modes clock timing figure 35. sdio clock timing (sdr modes) table 47. sdio bus clock timing parameters (sdr modes) parameter symbol minimum maximum unit comments ?t clk 40 ? ns sdr12 mode 20 ? ns sdr25 mode 10 ? ns sdr50 mode 4.8 ? ns sdr104 mode ?t cr , t cf ? 0.2 t clk ns t cr , t cf < 2.00 ns (max.) @100 mhz, c card = 10 pf t cr , t cf < 0.96 ns (max.) @208 mhz, c card = 10 pf clock duty cycle ? 30 70 % ? t clk t cr sdio_clk t cf t cr
document number: 002-15057 rev. *b page 95 of 110 cyw88335 device input timing figure 36. sdio bus input timing (sdr modes) table 48. sdio bus input timing parameters (sdr modes) symbol minimum maximum unit comments sdr104 mode t is 1.4 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v sdr50 mode t is 3.0 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v sdr25 mode t is 3.0 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v sdr12 mode t is 3.0 ? ns c card = 10 pf, vct = 0.975v t ih 0.8 ? ns c card = 5 pf, vct = 0.975v t is sdio_clk t ih cmd ? input dat[3:0] ? input
document number: 002-15057 rev. *b page 96 of 110 cyw88335 device output timing figure 37. sdio bus output ti ming (sdr modes up to 100 mhz) figure 38. sdio bus output timing (sdr modes 100 mhz to 208 mhz) table 49. sdio bus output timing parameters (sdr modes up to 100 mhz) symbol minimum maximum unit comments t odly ? 7.5 ns t clk 10 ns c l = 30 pf using driver type b for sdr50 t odly ? 14.0 ns t clk 20 ns c l = 40 pf using for sdr12, sdr25 t oh 1.5 ? ns hold time at the t odly (min) c l = 15 pf t odly sdio_clk t oh cmd ? output dat[3:0] ? output t clk t op sdio_clk cmd ? output dat[3:0] ? output t clk t odw
document number: 002-15057 rev. *b page 97 of 110 cyw88335 ? t op = +1550 ps for junction temperature of ? t op = 90 degrees during operation ? t op = ?350 ps for junction temperature of ? t op = ?20 degrees during operation ? t op = +2600 ps for junction temperature of ? t op = ?20 to +125 degrees during operation figure 39. ? t op consideration for variable data window (sdr 104 mode) table 50. sdio bus output timing parameters (sdr modes 100 mhz to 208 mhz) symbol minimum maximum unit comments t op 0 2 ui card output phase ? t op ?350 +1550 ps delay variation due to temp change after tuning t odw 0.60 ? ui t odw =2.88 ns @208 mhz 4 t op = 1550 ps sampling point after tuning 4 t op = C350 ps data valid window data valid window data valid window sampling point after card junction heating by +90c from tuning temperature sampling point after card junction cooling by C20c from tuning temperature
document number: 002-15057 rev. *b page 98 of 110 cyw88335 18.1.4 sdio bus timing specifications in ddr50 mode figure 40. sdio clock timing (ddr50 mode) table 51. sdio bus clock timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments ?t clk 20 ? ns ddr50 mode ?t cr ,t cf ? 0.2 tclk ns t cr , t cf < 4.00 ns (max) @50 mhz, c card = 10 pf clock duty cycle ? 45 55 % ? t clk t cr sdio_clk t cf t cr
document number: 002-15057 rev. *b page 99 of 110 cyw88335 data timing, ddr50 mode figure 41. sdio data timing (ddr50 mode) table 52. sdio bus timing parameters (ddr50 mode) parameter symbol minimum maximum unit comments input cmd input setup time t isu 6?nsc card < 10pf (1 card) input hold time t ih 0.8 ? ns c card < 10pf (1 card) output cmd output delay time t odly ?13.7nsc card < 30pf (1 card) output hold time t oh 1.5 ? ns c card < 15pf (1 card) input dat input setup time t isu2x 3?nsc card < 10pf (1 card) input hold time t ih2x 0.8 ? ns c card < 10pf (1 card) output dat output delay time t odly2x ? 7.0 ns c card < 25pf (1 card) output hold time t odly2x 1.5 ? ns c card < 15pf (1 card) t isu2x sdio_clk dat[3:0] ? input f pp t ih2x t isu2x t ih2x invalid invalid invalid invalid data data data data data data t odly2x ? (min) t odly2x ? (min) t odly2x ? (max) t odly2x ? (max) dat[3:0] ? output in ? ddr50 ? mode, ? dat[3:0] ? lines ? are ? sampled ? on ? both ? edges ? of ? the ? clock ? (not ? applicable ? for ? cmd ? line) available ? timing ? window ? for ? card ? output ? transition available ? timing ? window ? for ? host ? to ? sample ? data ? from ? card
document number: 002-15057 rev. *b page 100 of 110 cyw88335 18.1.5 gspi signal timing the gspi host and device always use the rising edge of clock to sample data. figure 42. gspi timing table 53. gspi timing parameters parameter symbol minimum maximum units note clock period t1 20.8 ? ns f max = 48 mhz clock high/low t2/t3 (0.45 t1) ? t4 (0.55 t1) ? t4 ns ? clock rise/fall time a a. limit applies when spi_clk = f max . for slower clock speeds, longer rise/fall times are acceptabl e provided that the transitions are monotonic and the setup and hold time limits are complied with. t4/t5 ? 2.5 ns measured from 10% to 90% of vddio input setup time t6 5.0 ? ns setup time, simo valid to spi_clk active edge input hold time t7 5.0 ? ns hold time, spi_clk active edge to simo invalid output setup time t8 5.0 ? ns setup time, somi valid before spi_clk rising output hold time t9 5.0 ? ns hold time, spi_clk active edge to somi invalid csx to clock b b. spi_csx remains active for entire duration of gspi read/write/write-read transaction (overall words for multiple-word transac tion). ? 7.86 ? ns csx fall to 1st rising edge clock to csx a ? ? ? ns last falling edge to csx high
document number: 002-15057 rev. *b page 101 of 110 cyw88335 18.2 jtag timing table 54. jtag timing characteristics signal name period output maximum output minimum setup hold tck 125 ns ? ? ? ? tdi ? ? ? 20 ns 0 ns tms ? ? ? 20 ns 0 ns tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
document number: 002-15057 rev. *b page 102 of 110 cyw88335 19. power-up sequence and timing 19.1 sequencing of reset and regulator control signals the cyw88335 has two signals that allow the host to control powe r consumption by enabling or disabling the bluetooth, wlan, and internal regulator blocks. these signals ar e described below. additionally, diagrams ar e provided to indica te proper sequencing of the signals for various operational states (see figure 43 , figure 44 on page 103 , and figure 45 and figure 46 on page 104 ). the timing values indicated are minimum required va lues; longer delays are also acceptable. 19.1.1 description of control signals wl_reg_on : used by the pmu to power up the wlan section. it is also or-gated with the bt_reg_on input to control the internal cyw88335 regulators. when this pin is high, the regulato rs are enabled and the wlan section is out of reset. when this pin is low the wlan section is in reset. if both the bt_r eg_on and wl_reg_on pins are lo w, the regulators are disabled. bt_reg_on : used by the pmu (or-gated with wl_reg_on) to powe r up the internal cyw88335 regulators. if both the bt_reg_on and wl_reg_on pins are low, the regulators are disabled. when this pin is low and wl_reg_on is high, the bt section is in reset. note: for both the wl_reg_on and bt_reg_on pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). this is to allow time for the cbuck regulator to discharge. if this delay is not followed, then there may be a vddio in-rush current on the order of 36 ma during the next pmu cold start. the cyw88335 has an internal power-on reset (por) circuit. the devi ce will be held in reset for a maximum of 110 ms after vddc and vddio have both passed the por threshold. wait at least 150 m s after vddc and vddio are available before initiating sdio accesses. ensure that bt_reg_on is driven high at the same time as or before wl_reg_on is driven high. bt_reg_on can be driven low 100 ms after wl_reg_on goes high. vbat should not rise 10%?90% faster than 40 microseconds. vbat sh ould be up before or at the same time as vddio. vddio should not be present first or be held high before vbat is high.
document number: 002-15057 rev. *b page 103 of 110 cyw88335 19.1.2 control signal timing diagrams figure 43. wlan = on, bluetooth = on figure 44. wlan = off, bluetooth = off 32.678 ? khz ? sleep ? clock vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 10 ? milliseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high. vbat* vddio wl_reg_on bt_reg_on 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 10 ? milliseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-15057 rev. *b page 104 of 110 cyw88335 figure 45. wlan = on, bluetooth = off figure 46. wlan = off, bluetooth = on vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 10 ? milliseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high. 3. ? ensure ? that ? bt_reg_on ? is ? driven ? high ? at ? the ? same ? time ? as ? or ? before ? wl_reg_on ? is ? driven ? high. ?? bt_reg_on ? can ? be ? driven ? low ? 100 ? ms ? after ? wl_reg_on ? goes ? high. 100 ms vbat* vddio wl_reg_on bt_reg_on 90% ? of ? vh ~ ? 2 ? sleep ? cycles 32.678 ? khz ? sleep ? clock *notes: 1. ? vbat ? should ? not ? rise ? 10%?90% ? faster ? than ? 40 ? microseconds ? or ? slower ? than ? 10 ? milliseconds. ? 2. ? vbat ? should ? be ? up ? before ? or ? at ? the ? same ? time ? as ? vddio. ? vddio ? should ? not ? be ? present ? first ? or ? be ? held ? high ? before ? vbat ? is ? high.
document number: 002-15057 rev. *b page 105 of 110 cyw88335 20. package information 20.1 package thermal characteristics 20.2 junction temperature estimation and psi jt versus theta jc package thermal characterization parameter psi?j t ( ? jt ) yields a better estimation of actual junction temperature (t j ) versus using the junction-to-case thermal resistance parameter theta?j c ( ? jc ). the reason for this is that ? jc assumes that all the power is dissipated through the top surface of the package case. in actual applications, some of the power is dissipated through the bot tom and sides of the package. ? jt takes into account power dissipated through the top, bottom, and sides of the package. the equation for calculating the device junction temperature is: t j = t t + p x ? jt where: t j = junction temperature at steady-state condition (c) t t = package case top center temperature at steady-state condition (c) p = device power dissipation (watts) ? jt = package thermal characteristics; no airflow (c/w) 20.3 environmental characteristics for environmental characteristics data, see table 25 on page 65 . table 55. package thermal characteristics a a. no heat sink, ta = 70c. this is an estimate, based on a 4- layer pcb that conforms to eia/jesd51?7 (101.6 mm 101.6 mm 1.6 mm) an d p = specified power maximum continuous power dissipation. characteristic wlbga ? ja (c/w) (value in still air) 32.9 ? jb (c/w) 2.56 ? jc (c/w) 0.98 ? jt (c/w) 3.30 ? jb (c/w) 9.85 maximum junction temperature t j (c) 125 maximum power dissipation (w) 1.119
document number: 002-15057 rev. *b page 106 of 110 cyw88335 21. mechanical information figure 47. 145-ball wlbga pack age mechanical information
document number: 002-15057 rev. *b page 107 of 110 cyw88335 figure 48. wlbga keep-out areas for pcb layout?bottom view with balls facing up note: no top-layer metal is allowed in keep-out areas.
document number: 002-15057 rev. *b page 108 of 110 cyw88335 22. ordering information 23. references the references in this section may be used in conjunction with this document. note: cypress provides customer access to technical documentatio n and software through its customer support portal (csp) and downloads & support site (see iot resources ). for cypress documents, replace the ?xx? in the document number with the largest number available in the repository to ensure that you have the most cu rrent version of the document. part number package description operating ambient tem- perature cyw88335l2cubg a a. cyw88335l2cubg offers an updated solder ball composition to improve thermal cycling performance. assembly processes are not a ffected. form, fit, and function are unchanged. 145 ball wlbga (4.87 mm 5.413 mm, 0.4 mm pitch) dual-band 2.4 ghz and 5 ghz wlan + bt 4.1 for automotive applications ?40c to +85c document (or item) name number source [1] bluetooth mws coexistence 2-wire transport interface specification ? www.bluetooth.com
document number: 002-15057 rev. *b page 109 of 110 cyw88335 document history document title: cyw88335 single-chip 5g wi-fi ieee 802.11ac mac/baseband/radi o with integrated bluetooth 4.1 for automotive applications document number: 002-15057 revision ecn orig. of change submission date description of change ** ? ? 09/23/2015 88335-ds100-r: initial release *a 5461640 utsv 10/20/2016 updated to cypress template *b 5730057 aesatmp7 05/08/2017 updated cypress logo and copyright.
document number: 002-15057 rev. *b revised may 8, 2017 page 110 of 110 cyw88335 ? cypress semiconductor corporation, 2015-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragra ph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modi fication, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks interface cypress.com/interface internet of things cypress.com/iot lighting & power control cypress.com/powerpsoc memory cypress.com/memory psoc cypress.com/psoc touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp | psoc 6 cypress developer community forums | wiced iot forums | projects | video | blogs | training | components technical support cypress.com/support 110

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